APF51 - Revision history

FabienM at 07:40, 12 February 2015

2015-02-12T07:40:43Z

2013-09-04T11:17:03Z

‎Description

2013-01-19T19:41:06Z

‎Feature list

2011-10-13T09:35:23Z

‎Resources

2011-09-13T18:27:03Z

‎Description

2011-08-15T22:08:45Z

‎Description

2011-06-25T08:46:13Z

‎Feature list

2011-06-20T09:42:51Z

‎Other

2011-05-04T15:45:11Z

‎Feature list

2011-03-03T16:52:05Z

‎Description

← Older revision		Revision as of 07:40, 12 February 2015
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		+	[[Category: APF51]]
	==Description==		==Description==
	The APF51 is a high-end [https://en.wikipedia.org/wiki/Single-board_computer Single Board Computer] targeted for advanced GUI, intensive computation and extended connectivity.		The APF51 is a high-end [https://en.wikipedia.org/wiki/Single-board_computer Single Board Computer] targeted for advanced GUI, intensive computation and extended connectivity.

@@ Line 1: / Line 1: @@
 ==Description==
-The APF51 is a high-end Single Board Computer targeted for advanced GUI, intensive computation and extended connectivity.
+The APF51 is a high-end [https://en.wikipedia.org/wiki/Single-board_computer Single Board Computer] targeted for advanced GUI, intensive computation and extended connectivity.
 Here is a list of the main features:

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 ===FPGA===
 * [[Using_FPGA]]
 [[Category:MainBoards]]
 [[Category:Hardware]]

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 ==Resources==
-* TBD
 ==Feature list==

@@ Line 16: / Line 16: @@
 * Supplies: high end DC/DC converters and LDOs on board. Only one external supply of 5V required.
 * Low power sleep mode
-* Mechanical dimensions: ~55x55mm (TBD)
+* Mechanical dimensions: ~58x59mm
 All the i.MX51 peripherals (LCD, 2xSDIO, 2xSPI, 6xSerial, I2C, CSI, 3xUSB, keypad, PWM, etc...) and the FPGA signals can be accessed through two high density [[Hirose connectors]].

@@ Line 24: / Line 24: @@
 ==Feature list==
 {| border="0" cellpadding="5" cellspacing="5" summary="Hardware Add-Ons by functionnalities"
 |----------------

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 * [[PWM]]: PWM output J2 pin 18 (2.8V output level if used)
 * [[GPIO_Driver]]
-* [[APF51_PMIC]]
+* [[APF51_PMIC]] (Touchscreen, RTC, LEDs, GPIOs, ADCs, Battery)
 ===FPGA===
 * [[Using_FPGA]]

@@ Line 4: / Line 4: @@
 Here is a list of the main features:
 * Processor: [http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=i.MX515 Freescale i.MX51] (Cortex-A8 @ 800MHz)
-* RAM: Mobile DDR. 64 to 512MB. 32 bits data bus. Default capacity will be 128MB or 256MB.
+* RAM: Mobile DDR 400. 64 to 512MB. 32 bits data bus. Default capacity will be 256MB.
 * Flash: Mobile NAND. 512MB, 8 bits data bus.
 * Ethernet: onboard Physical (ready to use Ethernet 10/100Mbit link)
 * USB: High speed USB OTG (OnTheGo) with onboard Physical (ready to use USB OTG link)
 * USB: 2 High speed Hosts with integrated PHY
-* RS232: onboard Physical (RS232 compatible interface)
+* FPGA: Xilinx Spartan 6 (LX9 or LX16). Default: LX9
-* FPGA: Xilinx Spartan 6
+* Touchscreen controler (4/5 wires)
-* Supplies: high end DC/DC converters and LDOs on board. Only one external supply of 3.3V required.
+* Low speed ADCs (up to 4)
 * Low power sleep mode
 * Mechanical dimensions: ~00x00mm (TBD)
-All the i.MX51 peripherals (LCD, 2xSDIO, 3xSPI, 6xSerial, I2C, CSI, 3xUSB, keypad, PWM, etc...) and the FPGA signals can be accessed through two high density [[Hirose connectors]].
+All the i.MX51 peripherals (LCD, 2xSDIO, 2xSPI, 6xSerial, I2C, CSI, 3xUSB, keypad, PWM, etc...) and the FPGA signals can be accessed through two high density [[Hirose connectors]].
 ==Resources==