APF6 SP Interfaces description - Revision history

FabienM at 11:42, 5 July 2021

2021-07-05T11:42:15Z

FabienM: /* Links */

2019-08-05T12:36:41Z

‎Links

FabienM: /* Links */

2019-08-05T12:36:35Z

‎Links

FabienM: /* Howto */

2017-08-23T13:28:07Z

‎Howto

FabienM: /* Howto */

2016-02-22T14:27:59Z

‎Howto

FabienM: /* Howto */

2016-02-22T14:02:12Z

‎Howto

FabienM: /* Introduction */

2016-02-03T08:25:53Z

‎Introduction

FabienM: /* Pinouts */

2016-02-03T08:16:49Z

‎Pinouts

FabienM at 08:15, 3 February 2016

2016-02-03T08:15:33Z

FabienM: Created page with " Category: APF6_SP Category: FPGA Category: CycloneV Category: Quartus Category: Qsys = Introduction = This page describe the FPGA interfaces for APF6_SP..."

2016-02-03T08:14:40Z

Created page with " Category: APF6_SP Category: FPGA Category: CycloneV Category: Quartus Category: Qsys = Introduction = This page describe the FPGA interfaces for APF6_SP..."

New page

[[Category: APF6_SP]]
[[Category: FPGA]]
[[Category: CycloneV]]
[[Category: Quartus]]
[[Category: Qsys]]

= Introduction =

This page describe the FPGA interfaces for APF6_SP.

= i.MX6 to CycloneV =

* [[IMX6-CycloneV interface description | IMX6-CycloneV interface description (PCIe)]]
= DDR3 to CycloneV =
* [[DDR3-CycloneV interface description | DDR3-CycloneV interface description]]

= Pinouts =
* [[APF6_SP hirose pinout | Pinout on apf6sp hirose connector]]

= Howto =

* [[APF6_SP_The_full_howto | The full FPGA howto for the APF6_sp, with PCIe, DDR3 and I/O]]

= Links =

← Older revision		Revision as of 12:36, 5 August 2019
Line 29:		Line 29:
	= Links =		= Links =

−	* [[Pci debug]]: a ~~tools~~ for read/write in PCIe BAR.	+	* [[Pci debug]]: a tool for read/write in PCIe BAR.

← Older revision		Revision as of 12:36, 5 August 2019
Line 28:		Line 28:

	= Links =		= Links =
		+
		+	* [[Pci debug]]: a tools for read/write in PCIe BAR.

← Older revision		Revision as of 13:28, 23 August 2017
Line 25:		Line 25:

	* [[APF6_SP_The_full_howto \| The full FPGA howto for the APF6_sp, with PCIe, DDR3 and I/O]]		* [[APF6_SP_The_full_howto \| The full FPGA howto for the APF6_sp, with PCIe, DDR3 and I/O]]
		+	* [[Qsys_USB_BLASTER_Jtag-avalon-MM \| Use JTaG USB-Blaster to access avalon bus memory on APF6_SP FPGA]]

	= Links =		= Links =

← Older revision		Revision as of 14:27, 22 February 2016
Line 25:		Line 25:

	* [[APF6_SP_The_full_howto \| The full FPGA howto for the APF6_sp, with PCIe, DDR3 and I/O]]		* [[APF6_SP_The_full_howto \| The full FPGA howto for the APF6_sp, with PCIe, DDR3 and I/O]]
−	* [[APF6_SP_DMA_simple_howto \| How to do simple DMA access]]

	= Links =		= Links =

← Older revision		Revision as of 14:02, 22 February 2016
Line 25:		Line 25:

	* [[APF6_SP_The_full_howto \| The full FPGA howto for the APF6_sp, with PCIe, DDR3 and I/O]]		* [[APF6_SP_The_full_howto \| The full FPGA howto for the APF6_sp, with PCIe, DDR3 and I/O]]
		+	* [[APF6_SP_DMA_simple_howto \| How to do simple DMA access]]

	= Links =		= Links =

@@ Line 15: / Line 15: @@
 * [[IMX6-CycloneV interface description | IMX6-CycloneV interface description (PCIe)]]
 * [[DDR3-CycloneV interface description | DDR3-CycloneV interface description]]
 = Pinouts =

← Older revision		Revision as of 08:25, 3 February 2016
Line 9:		Line 9:

	This page describe the FPGA interfaces for APF6_SP.		This page describe the FPGA interfaces for APF6_SP.
		+
		+	[[File:CycloneV_APF6_general.png\|frame\|center\|Global schematic of FPGA under APF6_SP]]

	= i.MX6 to CycloneV =		= i.MX6 to CycloneV =

@@ Line 18: / Line 18: @@
 = Pinouts =
 * [[APF6_SP hirose pinout | Pinout on apf6sp hirose connector]]
 = Howto =

@@ Line 1: / Line 1: @@
+[[Using_FPGA| << FPGA general page]]
 [[Category: APF6_SP]]
 [[Category: FPGA]]