DDR3-CycloneV interface description - Revision history

FabienM: /* Clock */

2017-09-21T11:21:59Z

‎Clock

2016-05-25T15:53:55Z

‎Parameters

2016-02-02T15:22:12Z

‎General description

2016-02-01T16:18:14Z

‎Downloads

2016-02-01T16:17:48Z

2016-02-01T15:20:59Z

‎Links

2016-02-01T15:19:58Z

‎Links

2016-02-01T15:19:14Z

‎UniPhy Howto

2016-02-01T15:18:45Z

‎UniPhy Howto

2016-02-01T15:18:05Z

‎UniPhy Howto

← Older revision		Revision as of 11:21, 21 September 2017
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	{{Note\| In one line :<pre class="host">$ find . -name "*_p0_pin_map.tcl" \| xargs sed -iolt "/_mem_if_ddr3_emif_0_p0_get_input_clk_id {/a return \$pll_output_node_id"</pre>}}		{{Note\| In one line :<pre class="host">$ find . -name "*_p0_pin_map.tcl" \| xargs sed -iolt "/_mem_if_ddr3_emif_0_p0_get_input_clk_id {/a return \$pll_output_node_id"</pre>}}
		+
		+	=== Failed to find PLL reference clock ===
		+
		+	It's a known intel bug documented [https://www.altera.com/support/support-resources/knowledge-base/solutions/rd05282014_665.html here].

	== IO ==		== IO ==

@@ Line 18: / Line 18: @@
 |DDR3L
 |-
-|Speed
+|Speed (DDR)
 |750Mhz
 |-

@@ Line 32: / Line 32: @@
 == General description ==
- {{Under_Construction}}
 Diagram below describe the connections between the CycloneV and the two DDR3 blocks. Each DDR3 blocks has two banks of 128MB, on one chip (U15) all data are used, and on the other chip, only 128MB are used, the second bank is not plugged. Thus, the amount of ram accessible via the fpga is 384MB, with a data bus of 24bits.

@@ Line 97: / Line 97: @@
 == Downloads ==
-Soon here, some example project to downloads.
+Soon here, some examples project to downloads.
 == Links ==

@@ Line 357: / Line 357: @@
 == Links ==
 * [http://www.alterawiki.com/wiki/Reference_Design_-_Cyclone_V_Hard_Memory_Controller_with_Avalon_MM_data_width_expanded_for_User_ECC Reference Design - Cyclone V Hard Memory Controller with Avalon MM data width expanded for User ECC]
 * [https://www.altera.com/support/support-resources/knowledge-base/solutions/rd05282014_665.html The Clock DDR3 hack on altera website]

← Older revision		Revision as of 15:19, 1 February 2016
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	== Links ==		== Links ==

		+	* [http://www.alterawiki.com/wiki/Reference_Design_-_Cyclone_V_Hard_Memory_Controller_with_Avalon_MM_data_width_expanded_for_User_ECC Reference Design - Cyclone V Hard Memory Controller with Avalon MM data width expanded for User ECC]
	* [https://www.altera.com/support/support-resources/knowledge-base/solutions/rd05282014_665.html The Clock DDR3 hack on altera website]		* [https://www.altera.com/support/support-resources/knowledge-base/solutions/rd05282014_665.html The Clock DDR3 hack on altera website]

@@ Line 66: / Line 66: @@
 ** Select checkbox '''Expand Avalon-MM data for ECC'''
 ** Select 48bits instead of 32
 {{Note| Using 48bits instead 32 is not standard for avalon it can be harder to connect inside your design}}

@@ Line 61: / Line 61: @@
 * Tab '''Memory parameters'''
 ** Memory device speed grade : 400Mhz
 ** Total interface width : 24
 ** Row address width : 14
 * Tab '''Controller Settings''' (Optionnal if you wan't to use the two DDR3 chip)