PCIe FPGA loading - Revision history

FabienM: /* Automatic FPGA configuration */

2016-02-05T09:59:46Z

‎Automatic FPGA configuration

2016-02-05T09:52:43Z

‎Automatic FPGA configuration

2016-02-05T09:45:58Z

‎Configure the FPGA

2015-08-27T06:42:24Z

‎Core configuration in Linux

2015-06-22T11:24:08Z

‎Introduction

2015-06-22T11:23:26Z

‎Quartus configuration

2015-03-17T10:23:32Z

2015-03-17T10:23:05Z

‎Core configuration in Linux

2015-03-17T10:21:51Z

‎Linux configuration

2015-03-17T10:21:25Z

‎Quartus configuration

← Older revision		Revision as of 09:59, 5 February 2016
Line 62:		Line 62:

	=== Automatic FPGA configuration ===		=== Automatic FPGA configuration ===
		+
		+	To let apf configure the FPGA automatically at boot we have to configure U-boot and Linux as seen in the following.

	==== U-boot ====		==== U-boot ====

@@ Line 63: / Line 63: @@
 === Automatic FPGA configuration ===
-See the [[Target_Software_Installation#APF6_SP | target software installation]] to know how to install a ''firmware autoload'' on APF6_SP.
+==== U-boot ====
 == Links ==

@@ Line 60: / Line 60: @@
 Altera CvP 0000:01:00.0: CvP successful, application layer now ready
 </pre>
 == Links ==

@@ Line 56: / Line 56: @@
 <pre class="apf">
 $ tftp -g -r binary.core.rbf 192.168.0.2
-$ modprobe fpgaloader
+$ load_fpga output_file.core.rbf
-$ mknod /dev/altera_cvp c 249 0
-$ cat output_file.core.rbf > /dev/altera_cvp
 Altera CvP 0000:01:00.0: Now starting CvP...
 Altera CvP 0000:01:00.0: CvP successful, application layer now ready

@@ Line 3: / Line 3: @@
 == Introduction ==
-On APF6_SP it's possible to use the PCI express bus to configure the FPGA (cycloneV). This article describe how to do that.
+On APF6_SP  PCI express bus is used to configure the FPGA (cycloneV). This article describe how to do that.
 == Generate files ==

@@ Line 9: / Line 9: @@
 === Quartus configuration ===
-Your design must include the PCIe and CvP components. Once the project synthesized, open the menu:
+Your design must include the [[IMX6-CycloneV_interface_description#Qsys_.28Quartus.29_:_Avalon-MM_Cyclone_V_Hard_IP_for_PCI_Express_configuration_.28CvP.29 | PCIe and CvP components]]. Once the project synthesized, open the menu:
 <pre class="config">
 File -> Convert Programming Files ...

← Older revision	Revision as of 10:23, 17 March 2015
(No difference)

@@ Line 26: / Line 26: @@
 === Linux configuration ===
-All drivers are already selected by default in buildroot configuration.
+All drivers are already selected by default in APF6's Buildroot configuration.
 == Configure the FPGA ==

@@ Line 9: / Line 9: @@
 === Quartus configuration ===
-Your design must include the PCIe and CvP components. Once the project synthesized, open the menu
+Your design must include the PCIe and CvP components. Once the project synthesized, open the menu:
 <pre class="config">
 File -> Convert Programming Files ...
@@ Line 19: / Line 19: @@
 * Click on '''Generate'''
-You will get two files :
+You will get two files:
-* '''binary.periph.rbf''': peripheral config file to be loaded via serial config bus with uboot
+* '''binary.periph.rbf''': peripheral config file to be loaded via serial config bus with U-Boot
 * '''binary.core.rbf''': core config file to be loaded via PCIe bus with Linux.