POD Interrupt handler - Revision history

WikiSysop: /* How it actually works on i.XML (APF9328) */

2011-01-27T13:53:29Z

‎How it actually works on i.XML (APF9328)

WikiSysop: /* How it actually works on i.XML */

2011-01-27T13:52:35Z

‎How it actually works on i.XML

FabienM at 08:45, 20 March 2009

2009-03-20T08:45:58Z

FabienM at 22:26, 14 December 2008

2008-12-14T22:26:59Z

FabienM: Per revue, thanks to JDaM

2008-12-14T22:24:58Z

Per revue, thanks to JDaM

FabienM: Interrupt handler moved to POD Interrupt handler

2008-12-14T22:16:39Z

Interrupt handler moved to POD Interrupt handler

FabienM: New page: = Interrupt handler mechanism = This page details the software mechanism we have to implement in the CPU connected to the FPGA, to handle the multiple IP interrupt sources with only one i...

2008-12-12T14:46:34Z

New page: = Interrupt handler mechanism = This page details the software mechanism we have to implement in the CPU connected to the FPGA, to handle the multiple IP interrupt sources with only one i...

New page

= Interrupt handler mechanism =

This page details the software mechanism we have to implement in the CPU connected to the FPGA, to handle the multiple IP interrupt sources with only one interrupt physical signal.
Althought dedicated to Linux on ARM9, it should applies to every "well coded" OSes.

==Preamble==

ARM cores handle only 2 interrupts by default:
* FIQ: "Fast interrupt", highest priority one
* NIQ: "Normal interrupt"

Then constructors add their own logic to extend the number of interrupts connected to these 2 ones.

So on ARM systems there is a global interrupt handler which is called each time an interrupt occurs.
Its job is to identify the interrupt source and then to delegate the job to the sub "interrupt handler".

Linux integrates this mechanism and provides an API to handle multiple interrupt handler registering and IT dispatching:
<source lang="bash">
set_irq_chip(irq, struct irq_chip*);
set_irq_handler(irq, handler);
set_irq_flags(irq, flad);
set_irq_chained_handler(muxed_irq, demux_handler);
set_irq_chained_handler(muxed_irq, demux_handler);
...
</source>

==How it actually works on i.XML==

Interrupts are divided in 2 categories:
* i.MXL internal peripheral interrupts ("MPU"), with attributed numbers between 0 and 64
* GPIO interrupts ("GPIO"), with attributed numbers between 65 and 192 (32x 4 GPIO ports)

On a running system:
<source lang="bash">
# cat /proc/interrupts
CPU0
26: 0 MPU IMX-uart
29: 183 MPU IMX-uart
30: 495 MPU IMX-uart
35: 4592 MPU imx-mmc
39: 1 MPU I2C_IMX
40: 56534 MPU spi_imx.2
41: 0 MPU spi_imx.1
59: 326869 MPU i.MX Timer Tick
60: 0 MPU DMA
61: 1405 MPU DMA
110: 935 GPIO eth0
168: 6517 GPIO tsc2102
Err: 0
</source>

The ''GPIO'' family interrupts can be seen as a subclass of MPU interrupts (ITs). Indeed there is only one hardware interrupt per GPIO ports.
*GPIO_INT_PORTA has number 11
*GPIO_INT_PORTB has number 12
*GPIO_INT_PORTC has number 13
*GPIO_INT_PORTD has number 62

So, GPIO ITs are multiplexed for each port. Linux allows to have a "virtual" interrupt number, not reflecting the hardware one and which remove demultiplexing handling from the peripheral drivers.
This mechanism is used for handling POD single IT.

==How to implement it for POD==
We will declare IT 65 as a chained IRQ (if possible as it's already a virtual interrupt of IT 11) and add a demultiplexer for FPGA in the IRQ handler.
This way usable IT numbers for IP will be in the range [192-255?].

[[image:pod_interrupt.png|center|frame|'''figure 1''' - ''i.MX IRQ schematic'']]
===Interrupt register in the FPGA===
To handle the interrupts, the IT manager IP will have 2 registers:
* an Interrupt Mask Register (IMR) for interrupt activation/deactivation. Actually this is a 16 bits register at address 0x00 with 1 bit per IT -> 16 IT handled:
{| border="0" cellpadding="5" cellspacing="0" summary="FPGA IMR"
|- style="background:#efefef;"
|----------------
| '''FPGA_IMR''' || colspan="13" align="center" | Interrupt Mask Register || colspan="3" align="right" | '''Addr 0x0000'''
|---------------- align="center"
| BIT || 15 || 14 || 13 || 12 || 11 || 10 || 9 || 8 || 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
|---------------- align="center"
| || style="border:1px solid black;" | IT_15 || style="border:1px solid black;" | IT_14 || style="border:1px solid black;" | IT_13 || style="border:1px solid black;" | IT_12 || style="border:1px solid black;" | IT_11 || style="border:1px solid black;" | IT_10 || style="border:1px solid black;" | IT_9 || style="border:1px solid black;" | IT_8 || style="border:1px solid black;" | IT_7 || style="border:1px solid black;" | IT_6 || style="border:1px solid black;" | IT_5 || style="border:1px solid black;" | IT_4 || style="border:1px solid black;" | IT_3 || style="border:1px solid black;" | IT_2 || style="border:1px solid black;" | IT_1 || style="border:1px solid black;" | IT_0
|---------------- align="center"
| TYPE || rw || rw || rw || rw || rw || rw || rw || rw || rw || rw || rw || rw || rw || rw || rw || rw
|---------------- align="center"
| rowspan="2" | RESET || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0
|----------------
| colspan="17" align="center" | 0x0000
|-
|}

{| border="1" cellpadding="5" cellspacing="0" summary="FPGA IMR"
|- align="center"
! Name || Description || Settings
|----------------
| Bit 15-0 || Enable/disable corresponding interrupt || 0 -> IT masked/deactivated <br> 1 -> IT enabled
|----------------
|}
<br>
* an Interrupt Status Register (ISR) which holds the number of the IT generating the interrupt:
{| border="0" cellpadding="5" cellspacing="0" summary="FPGA ISR"
|- style="background:#efefef;"
|----------------
| '''FPGA_ISR''' || colspan="13" align="center" | Interrupt Status Register || colspan="3" align="right" | '''Addr 0x0002'''
|---------------- align="center"
| BIT || 15 || 14 || 13 || 12 || 11 || 10 || 9 || 8 || 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0
|---------------- align="center"
| || style="border:1px solid black;" | IT_15 || style="border:1px solid black;" | IT_14 || style="border:1px solid black;" | IT_13 || style="border:1px solid black;" | IT_12 || style="border:1px solid black;" | IT_11 || style="border:1px solid black;" | IT_10 || style="border:1px solid black;" | IT_9 || style="border:1px solid black;" | IT_8 || style="border:1px solid black;" | IT_7 || style="border:1px solid black;" | IT_6 || style="border:1px solid black;" | IT_5 || style="border:1px solid black;" | IT_4 || style="border:1px solid black;" | IT_3 || style="border:1px solid black;" | IT_2 || style="border:1px solid black;" | IT_1 || style="border:1px solid black;" | IT_0
|---------------- align="center"
| TYPE || rw || rw || rw || rw || rw || rw || rw || rw || rw || rw || rw || rw || rw || rw || rw || rw
|---------------- align="center"
| rowspan="2" | RESET || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0
|----------------
| colspan="17" align="center" | 0x0000
|-
|}

{| border="1" cellpadding="5" cellspacing="0" summary="FPGA IMR"
|- align="center"
! Name || Description || Settings
|----------------
| Bit 15-0 || Indicate whether the corresponding IT is pending or not. <br> Writing a 1 to this bit acknowledges the IT and clears it. || 0 -> IT not pending <br> 1 -> IT pending
|----------------
|}

==Links==
* [http://linux.omap.com/pipermail/linux-omap-open-source/2007-April/009545.html They have done it by module...]

@@ Line 27: / Line 27: @@
 </source>
-==How it actually works on i.XML (APF9328) ==
+==How it currently works on i.XML (APF9328) ==
 Interrupts are divided in 2 categories:

← Older revision		Revision as of 08:45, 20 March 2009
Line 124:		Line 124:
	==Links==		==Links==
	* [http://linux.omap.com/pipermail/linux-omap-open-source/2007-April/009545.html They have done it by module...]		* [http://linux.omap.com/pipermail/linux-omap-open-source/2007-April/009545.html They have done it by module...]
		+	[[Category:POD]]

← Older revision		Revision as of 22:26, 14 December 2008
Line 1:		Line 1:
−	= Interrupt handler mechanism =	+
		+	= Interrupt handler mechanism =

	This page details the software mechanism we have to implement in the CPU connected to the FPGA, to handle the multiple IP interrupt sources with only one interrupt physical signal.		This page details the software mechanism we have to implement in the CPU connected to the FPGA, to handle the multiple IP interrupt sources with only one interrupt physical signal.

@@ Line 1: / Line 1: @@
 = Interrupt handler mechanism =
 This page details the software mechanism we have to implement in the CPU connected to the FPGA, to handle the multiple IP interrupt sources with only one interrupt physical signal.
@@ Line 15: / Line 15: @@
 Its job is to identify the interrupt source and then to delegate the job to the sub "interrupt handler".
-Linux integrates this mechanism and provides an API to handle multiple interrupt handler registering and IT dispatching:
+Linux integrates this mechanism and provides an API to handle multiple
 <source lang="bash">
   set_irq_chip(irq, struct irq_chip*);
@@ Line 91: / Line 92: @@
 |----------------
 |}
 <br>
 * an Interrupt Status Register (ISR) which holds the number of the IT generating the interrupt:
 {| border="0" cellpadding="5" cellspacing="0" summary="FPGA ISR"

← Older revision	Revision as of 22:16, 14 December 2008
(No difference)