Using FPGA - Revision history

FabienM: /* Design Tools */

2019-11-12T13:45:06Z

‎Design Tools

2019-04-29T13:23:05Z

‎CactusII

2019-04-29T13:22:54Z

‎Automatize FPGA design making

2019-04-29T13:18:09Z

‎Synthesizable Synchronous HDL

2019-04-29T13:12:56Z

‎Design Tools

2019-03-20T08:57:50Z

‎Automatize FPGA design making

2018-10-30T13:41:17Z

‎Design Tools

2018-10-15T10:03:13Z

‎Developing on the APF FPGA

2018-09-13T07:11:10Z

‎Chisel

2018-09-13T07:01:29Z

‎Links

@@ Line 50: / Line 50: @@
 '''Altera'''
-* [[Quartus | Quartus Web edition (Altera's free devt tool)]]
+* [[Quartus | Quartus Prime (Altera/Intel's free devt tool)]]
 * [[Modelsim-Altera | Install Modelsim-Altera (starter edition)]]

@@ Line 74: / Line 74: @@
 FuseSoC is a builder written in Python used to automatize FPGA constructions
-==== [[CactusII]] ====
+==== CactusII ====
 [http://funbase.cs.tut.fi/ Graphical IDE] for managing FPGA/ASIC design with IPX-ACT standard.

@@ Line 73: / Line 73: @@
 ==== [[FuseSoC]] ====
 FuseSoC is a builder written in Python used to automatize FPGA constructions
 | width="50%" |

@@ Line 97: / Line 97: @@
 ==== [[Chisel]] ====
-With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthezis. Armadeus system can help you to integrate a Chisel project on Armadeus board.
+With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthesis. Armadeus system can help you to integrate a Chisel project on Armadeus board.
 |----------------

@@ Line 59: / Line 59: @@
 '''Microsemi'''
-* [[Libero | Install Libero]]
+* [http://www.fabienm.eu/flf/installing-libero-on-debian-9/ Install Libero]
 |----------------

← Older revision		Revision as of 13:41, 30 October 2018
Line 58:		Line 58:
	* [[Diamond \| Install Lattice Diamond]]		* [[Diamond \| Install Lattice Diamond]]

		+	'''Microsemi'''
		+	* [[Libero \| Install Libero]]

	\|----------------		\|----------------

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 For complex projects, POD should be used to simplify design.
 | width="50%" |
 ===VHDL ===
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 * [http://iverilog.icarus.com/ Icarus] Famous open-source verilog simulator
 * [https://symbiyosys.readthedocs.io/en/latest/ SymbiYosys] open-source Verilog formal verification
 |----------------

@@ Line 109: / Line 109: @@
 * [https://www.altera.com/products/fpga/cyclone-series/cyclone-v/overview.html CycloneV overview from altera]
 | width="50%" |
 |}