Difference between revisions of "Using FPGA"
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| − | === | + | === FPGA Interfaces === |
| − | + | ||
| + | * APF9328 : [[IMX9328-Spartan3 interface description]] | ||
| + | * APF27 : [[IMX27-Spartan3A interface description]] | ||
| + | * APF51 : [[IMX51-Spartan6 interface description]] | ||
| + | * APF6SP: | ||
| + | ** [[IMX6-CycloneV interface description | IMX6-CycloneV interface description (PCIe)]] | ||
| + | ** [[DDR3-CycloneV interface description | DDR3-CycloneV interface description]] | ||
| + | ** [[APF6_SP hirose pinout | Pinout on apf6sp hirose connector]] | ||
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| − | + | ===Using Armadeus FPGA=== | |
| − | * [[ | + | Manage the FPGA from Armadeus distribution. |
| − | * [[ | + | |
| − | + | * [[Configure or flash FPGA ?]] | |
| − | + | * Configure the FPGA [[FPGA_loader | from Linux]], [[Target_Software_Installation#FPGA_firmware_test | from U-Boot]], [[PCIe_fpga_load | from PCIe]]. | |
| − | + | * Flashing FPGA firmware [[Uboot_FPGA_firmware_update_from_Linux | from Linux]], [[Target_Software_Installation#FPGA_firmware_installation | from U-Boot]] | |
| − | * [[ | + | * [[FPGA_register | Access the FPGA address domain from Linux]] |
| − | * [[ | + | |
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| − | + | === Make some examples === | |
| − | === | + | |
These examples give the basis to make VHDL design for FPGA. | These examples give the basis to make VHDL design for FPGA. | ||
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| − | === | + | === Design Tools=== |
| − | + | Description of tools used to simulate, to synthesize, and to download/configure FGPA. | |
| − | * [[ | + | '''Xilinx''' |
| − | * | + | * [[ISE WebPack installation on Linux| ISE WebPack (Xilinx's free devt tool) installation]] |
| − | * | + | * [[Vivado installation on Linux]] |
| − | * [[ | + | * [[How_to_make_a_VHDL_design_in_Ubuntu/Debian| How to setup the FPGA toolchain in Ubuntu/Debian]] |
| + | * [[How to simulate post synthesis and post place & route design with GHDL]] | ||
| + | '''Altera''' | ||
| + | * [[Quartus | Quartus Web edition (Altera's free devt tool)]] | ||
| + | * [[Modelsim-Altera | Install Modelsim-Altera (starter edition)]] | ||
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| − | === | + | === Automatize FPGA design making === |
==== [[Peripherals On Demand]] ==== | ==== [[Peripherals On Demand]] ==== | ||
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With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis. | With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis. | ||
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==== [[Chisel]] ==== | ==== [[Chisel]] ==== | ||
With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthezis. | With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthezis. | ||
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=== Verilog === | === Verilog === | ||
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''' CycloneV''' | ''' CycloneV''' | ||
* [https://www.altera.com/products/fpga/cyclone-series/cyclone-v/overview.html CycloneV overview from altera] | * [https://www.altera.com/products/fpga/cyclone-series/cyclone-v/overview.html CycloneV overview from altera] | ||
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Revision as of 14:06, 1 February 2016
Developing on the APF FPGA
FPGA Interfaces
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Using Armadeus FPGAManage the FPGA from Armadeus distribution.
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Make some examplesThese examples give the basis to make VHDL design for FPGA.
|
Design ToolsDescription of tools used to simulate, to synthesize, and to download/configure FGPA. Xilinx
Altera
|
Automatize FPGA design makingPeripherals On DemandFor complex projects, POD should be used to simplify design. MigenWith migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis. ChiselWith Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthezis. |
VHDL
Verilog |
LinksSome useful links. Wishbone Spartan CycloneV |
