Difference between revisions of "Using FPGA"

FPGA Interfaces

• APF9328: IMX9328-Spartan3 interface description
• APF27: IMX27-Spartan3A interface description
• APF51: IMX51-Spartan6 interface description
• APF6_SP: APF6_SP Interfaces description
• OPOS6UL_SP: OPOS6UL_SP Interfaces description

Using Armadeus FPGA

Manage the FPGA from Armadeus distribution.

• Configure the FPGA from Linux, from U-Boot, from PCIe.
• Flashing FPGA firmware from Linux, from U-Boot
• Access the FPGA address domain from Linux

Make some examples

These examples give the basis to make VHDL design for FPGA.

• LED
• Complete example with button and led on wishbone bus communication and Linux drivers

Design Tools

Description of tools used to simulate, to synthesize, and to download/configure FGPA.

Xilinx

• ISE WebPack and Vivado

Altera

• Quartus Web edition (Altera's free devt tool)
• Install Modelsim-Altera (starter edition)

Lattice

• Install IceCube
• Install Lattice Diamond

Automatize FPGA design making

Peripherals On Demand

For complex projects, POD should be used to simplify design.

HDL

VHDL

• VHDL coding styles & externals documentations
• Nice ideas/examples to look at
• www.opencores.org
• An Introductory VHDL Tutorial

Verilog

• Verilator an High speed verilog simulator
• Icarus Famous open-source verilog simulator
• SymbiYosys open-source Verilog formal verification

Synthesizable Synchronous HDL

Migen

With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis.

Chisel

With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthezis. Armadeus system can help you to integrate a Chisel project on Armadeus board.

Links

Some useful links.

Wishbone

• official Wishbone specifications
• Wikipedia Wishbone doc

Spartan

• Spartan-3 FPGA Family Data Sheet

CycloneV

• CycloneV overview from altera

OpenSource

• OpenSource FPGA map