|
|
| (One intermediate revision by the same user not shown) |
| Line 1: |
Line 1: |
| − | {{Under_Construction}}
| |
| | | | |
| − | Here is a simple use case example for POD. We will create a project to include a full modem UART coming from OpenCores.org. This IP is compatible with the [[OpenCore_16550_IP_Linux_driver|16550 Linux serial driver]]. The platform used is the APF9328.
| |
| − |
| |
| − |
| |
| − | [[image:projectuart.png|center|thumb|500px|'''figure 1''' - ''Simple example with one uart'']]
| |
| − |
| |
| − | In this example, a complete POD project is built including the synthesis, the simulation and the generation of the Linux drivers. The operating system used to run POD is Ubuntu 7.10.
| |
| − |
| |
| − | == Project creation ==
| |
| − |
| |
| − | In a terminal, run POD as follow:
| |
| − |
| |
| − | <source lang="bash">
| |
| − | $ python pod.py
| |
| − | POD>
| |
| − | </source>
| |
| − |
| |
| − | The runtime file ''pod.py'' is in directory ''pod/bin/''.
| |
| − |
| |
| − | A console prompt is displayed. To create a project, enter in the project environment
| |
| − | then write ''create'':
| |
| − |
| |
| − | <source lang="bash">
| |
| − | POD> project
| |
| − | POD.project> create uartproject
| |
| − | Project uartproject created
| |
| − | POD.project:uartproject>
| |
| − | </source>
| |
| − |
| |
| − | The project created is named ''uartproject''. Now, the targeted platform can be selected with the ''selectplatform'' command:
| |
| − |
| |
| − | <source lang="bash">
| |
| − | POD.project:uartproject> selectplatform apf9328
| |
| − | Component platform added as apf9328
| |
| − | Component imx9328_wb16_wrapper added as imx9328_wb16_wrapper00
| |
| − | Component rstgen_syscon added as rstgen_syscon00
| |
| − | Component irq_mngr added as irq_mngr00
| |
| − | setting base address 0x0 for irq_mngr00.swb16
| |
| − | Platform apf9328 selected
| |
| − | POD.project:uartproject>
| |
| − | </source>
| |
| − |
| |
| − | When the platform APF9328 is selected, POD automatically loads some components : the wrapper, the syscon and the interrupts manager corresponding to this platform. These components are used for a Wishbone bus. If they are not required they can be deleted with the ''delcomponent'' command.
| |
| − |
| |
| − | To complete the project, the uart16550 component must be loaded. The component library proposes severals components categories that can be displayed with the ''listcomponent'' command:
| |
| − |
| |
| − | <source lang="bash">
| |
| − | POD.project:uartproject> listcomponents
| |
| − | syscons wrappers test components
| |
| − | </source>
| |
| − |
| |
| − | UART components can be found in "components" category :
| |
| − |
| |
| − | <source lang="bash">
| |
| − | POD.project:uartproject> listcomponents components
| |
| − | i2cocore button irq_mngr led uart16550 ledsensor simplegpio
| |
| − | </source>
| |
| − |
| |
| − | A component can then be load with the ''addcomponent'' command:
| |
| − | <source lang="bash">
| |
| − | POD.project:uartproject> addinstance components.uart16550 uart
| |
| − | Component uart16550 added as uart
| |
| − | </source>
| |
| − |
| |
| − | Now that all the components of the project are loaded, we can connect them.
| |
| − |
| |
| − | == Component connection ==
| |
| − |
| |
| − | === Interrupt connection ===
| |
| − |
| |
| − | The UART component has one connection pin named ''interrupt.int_o'', it will be connected to the irqport pin 0 of the interrupt manager (irq_mngr00):
| |
| − |
| |
| − | <source lang="bash">
| |
| − | uartproject> connectpin uart.interrupt.int_o irq_mngr00.irq.irqport.0
| |
| − | pin connected
| |
| − | </source>
| |
| − |
| |
| − | === FPGA connections ===
| |
| − |
| |
| − | The UART signals must be connected outside the fpga. The platform name is used like another component of the project. The UART pins will be connected to the platform pins ''via'' the apf9328 instance.
| |
| − |
| |
| − | <source lang="bash">
| |
| − | POD.project:uartproject> connectpin uart.uart.srx_pad_i apf9328.fpga.IO_L21N_2
| |
| − | POD.project:uartproject> connectpin uart.uart.stx_pad_o apf9328.fpga.IO_L21P_2
| |
| − | POD.project:uartproject> connectpin uart.uart.rts_pad_o apf9328.fpga.IO_L22N_2
| |
| − | POD.project:uartproject> connectpin uart.uart.cts_pad_i apf9328.fpga.IO_L22P_2
| |
| − | POD.project:uartproject> connectpin uart.uart.dtr_pad_o apf9328.fpga.IO_L23N_2
| |
| − | POD.project:uartproject> connectpin uart.uart.dsr_pad_i apf9328.fpga.IO_L23P_2
| |
| − | POD.project:uartproject> connectpin uart.uart.dcd_pad_i apf9328.fpga.IO_L24N_2
| |
| − | POD.project:uartproject> connectpin uart.uart.ri_pad_i apf9328.fpga.IO_L40N_2
| |
| − | </source>
| |
| − |
| |
| − | === Bus connection ===
| |
| − |
| |
| − | The irq manager was automaticaly connected to the wrapper/syscon when the platform was selected (part of the plateform), thus only the UART must be connected to the wrapper with the ''connectbus'' command:
| |
| − |
| |
| − | <source lang="bash">
| |
| − | POD.project:uartproject> connectbus imx9328_wb16_wrapper00.mwb16 uart.swb16
| |
| − | Bus connected
| |
| − | </source>
| |
| − |
| |
| − | === Clock connection ===
| |
| − |
| |
| − | The Wishbone bus requires a clock and a reset connection to be assigned, this can be done by means of the ''addbusclock'' command.
| |
| − |
| |
| − | <source lang="bash">
| |
| − | > addbusclock rstgen_syscon00.candr imx9328_wb16_wrapper00.mwb16
| |
| − | Connected
| |
| − | </source>
| |
| − |
| |
| − | This connection is done automatically when command ''autoconnectbus'' is called.
| |
| − |
| |
| − | == Code generation ==
| |
| − |
| |
| − | The component connections are now done. The Intercon and the Top components
| |
| − | can then be automatically generated.
| |
| − |
| |
| − | === Intercon ===
| |
| − |
| |
| − | The intercon is a component creating the connections for the Wishbone bus. It is generated with the ''intercon'' command and with the master bus interface as parameter :
| |
| − |
| |
| − | <source lang="bash">
| |
| − | POD.project:uartproject> intercon imx9328_wb16_wrapper00.mwb16
| |
| − | setting base address 0x10 for uart.swb16
| |
| − | Component imx9328_wb16_wrapper00_mwb16_intercon added as
| |
| − | imx9328_wb16_wrapper00_mwb16_intercon
| |
| − | Intercon with name : imx9328_wb16_wrapper00_mwb16_intercon Done
| |
| − | </source>
| |
| − |
| |
| − | A new component named ''imx9328_wb16_wrapper00_mwb16_intercon'' is created and added to the project.
| |
| − |
| |
| − | === Top ===
| |
| − |
| |
| − | The Top component is a VHDL component creating the non Wishbone connections. To generate it just type ''top'' :
| |
| − |
| |
| − | <source lang="bash">
| |
| − | POD.project:uartproject> top
| |
| − | Top generated with name : top_uartproject.vhd
| |
| − | </source>
| |
| − |
| |
| − | == Toolchain project generation ==
| |
| − |
| |
| − | The project is now fully specified, we can generate the project files for the synthesis, for the simulation and for the driver.
| |
| − |
| |
| − | === Synthesis ===
| |
| − |
| |
| − | The targeted FPGA is a Xilinx Spartan3 and thus ISE is needed for the synthesis. Under the ''synthesis'' environment ISE can be selected with the ''selecttoolchain'' command :
| |
| − |
| |
| − | <source lang="bash">
| |
| − | POD.project:uartproject> synthesis
| |
| − | POD.project.synthesis> selecttoolchain ise
| |
| − | </source>
| |
| − |
| |
| − | Then the synthesis project can be generated :
| |
| − |
| |
| − | <source lang="bash">
| |
| − | POD.project.synthesis> generateproject
| |
| − | Make directory for imx9328_wb16_wrapper
| |
| − | Make directory for rstgen_syscon
| |
| − | Make directory for irq_mngr
| |
| − | Make directory for uart16550
| |
| − | Make directory for imx9328_wb16_wrapper00_mwb16_intercon
| |
| − | POD.project.synthesis> generatepinout
| |
| − | Constraint file generated with name :
| |
| − | uartproject/synthesis/uartproject.ucf
| |
| − | POD.project.synthesis> generatetcl
| |
| − | Script generated with name uartproject.tcl
| |
| − | </source>
| |
| − |
| |
| − | The ''generateproject'' command creates a subdirectory for each component and fill in it with the corresponding VHDL code.
| |
| − | ''generatepinout'' command creates the constraint file for the fpga-pin configuration and ''generatetcl'' creates the tcl script to automatise ISE.
| |
| − |
| |
| − | In ISE, to synthesize the project we just have to launch :
| |
| − | <source lang="bash">
| |
| − | % source uartproject.tcl
| |
| − | </source>
| |
| − |
| |
| − |
| |
| − | ===Simulation project===
| |
| − | TBD
| |
| − |
| |
| − | === Driver generation ===
| |
| − |
| |
| − | To generate the driver, the operating system must be selected :
| |
| − | <source lang="bash">
| |
| − | POD.project:uartproject> driver
| |
| − | POD.project.driver> selectoperatingsystem linux
| |
| − | </source>
| |
| − |
| |
| − | Then command ''generateproject'' can be used to create the driver project:
| |
| − | <source lang="bash">
| |
| − | POD.project.driver> generateproject
| |
| − | No driver for imx9328_wb16_wrapper
| |
| − | No driver for rstgen_syscon
| |
| − | Copy drivers template for irq_mngr
| |
| − | Copy drivers template for uart16550
| |
| − | No driver for imx9328_wb16_wrapper00_mwb16_intercon
| |
| − | </source>
| |
| − |
| |
| − | For each component in the project, POD looks for a template driver according to the OS selected (here Linux). If a template is found, the files are copied in the ''project/drivers/'' directory.
| |
| − | In this example, only the ''irq_mngr'' and the ''uart16550'' have a linux driver.
| |
| − |
| |
| − | Once the template sources copied, they can be filled in with the ''filltemplates'' command :
| |
| − |
| |
| − | <source lang="bash">
| |
| − | POD.project.driver> filltemplates
| |
| − | Fill template for irq_mngr
| |
| − | Fill template for uart16550
| |
| − | </source>
| |
| − |
| |
| − | The drivers will be copied in the Armadeus project tree with the command ''copydrivers''. But before, the driver directory must be selected with the ''selectprojecttree'' command:
| |
| − |
| |
| − | <source lang="bash">
| |
| − | ...> selectprojecttree ~/armadeus/target/linux/modules/fpga/POD
| |
| − | POD.project:uartproject.driver> copydrivers
| |
| − | </source>
| |
| − |
| |
| − | == Script ==
| |
| − |
| |
| − | Scripts can be used to automatize the conception of a project.
| |
| − | A script is a simple text file with one command per line. The # symbol can be used for delimiting comments.
| |
| − |
| |
| − | Scripts can be launched directly from the command line when calling POD:
| |
| − |
| |
| − | <source lang="bash">
| |
| − | $ python pod.py scriptname
| |
| − | </source>
| |
| − |
| |
| − | Or can be loaded from POD :
| |
| − | <source lang="bash">
| |
| − | POD> source scriptname
| |
| − | </source>
| |
| − |
| |
| − | Finally a command history can be saved as a script with the ''savehistory'' command :
| |
| − |
| |
| − | <source lang="bash">
| |
| − | POD> savehistory uartscript
| |
| − | </source>
| |
| − |
| |
| − | The whole script for the uart project example can be found below :
| |
| − | <source lang="bash">
| |
| − | project.create uartproject
| |
| − | project.selectplatform apf9328
| |
| − | project.listcomponents
| |
| − | project.listcomponents components
| |
| − | project.addcomponent components.uart16550 uart
| |
| − | project.connectpin uart.interrupt.int_o irq_mngr00.irq.irqport.0
| |
| − | project.connectpin uart.uart.srx_pad_i apf9328.fpga.IO_L21N_2
| |
| − | project.connectpin uart.uart.stx_pad_o apf9328.fpga.IO_L21P_2
| |
| − | project.connectpin uart.uart.rts_pad_o apf9328.fpga.IO_L22N_2
| |
| − | project.connectpin uart.uart.cts_pad_i apf9328.fpga.IO_L22P_2
| |
| − | project.connectpin uart.uart.dtr_pad_o apf9328.fpga.IO_L23N_2
| |
| − | project.connectpin uart.uart.dsr_pad_i apf9328.fpga.IO_L23P_2
| |
| − | project.connectpin uart.uart.dcd_pad_i apf9328.fpga.IO_L24N_2
| |
| − | project.connectpin uart.uart.ri_pad_i apf9328.fpga.IO_L40N_2
| |
| − | project.connectbus imx9328_wb16_wrapper00.mwb16 uart.swb16
| |
| − | project.addbusclock rstgen_syscon00.candr imx9328_wb16_wrapper00.mwb16
| |
| − | project.intercon imx9328_wb16_wrapper00.mwb16
| |
| − | project.codegen.intercon imx9328_wb16_wrapper00.mwb16
| |
| − | project.codegen.top
| |
| − | project.synthesis.selecttoolchain ise
| |
| − | project.synthesis.generateproject
| |
| − | project.synthesis.generatepinout
| |
| − | project.synthesis.generatetcl
| |
| − | project.simulation.selecttoolchain ghdl
| |
| − | project.simulation.generatetestbench
| |
| − | project.simulation.generatemakefile
| |
| − | project.driver.selectoperatingsystem linux
| |
| − | project.driver.generateproject
| |
| − | project.driver.filltemplates
| |
| − | project.driver.selectprojecttree ~/armadeus/target/linux/modules/fpga/POD
| |
| − | project.driver.copydrivers
| |
| − | </source>
| |
| − | [[Category:POD]]
| |
