Difference between revisions of "Pci debug"
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'''pci_debug''' is a useful tool meant to access PCIe BARx memory from userspace. | '''pci_debug''' is a useful tool meant to access PCIe BARx memory from userspace. | ||
| − | = Buildroot configuration = | + | == Buildroot configuration == |
| − | + | * Should be done by default on [[APF6_SP]] | |
| − | * | + | * Select pci_debug: |
<pre class="config"> | <pre class="config"> | ||
Target packages ---> | Target packages ---> | ||
| − | + | Hardware handling ---> | |
| − | + | [*] pcidebug | |
| − | + | ||
</pre> | </pre> | ||
| − | * | + | * then rebuild your BSP: |
| − | <pre class=" | + | <pre class="host"> |
| − | + | $ make | |
| − | + | ||
| − | + | ||
</pre> | </pre> | ||
| − | |||
| − | |||
= Using pci_debug = | = Using pci_debug = | ||
| Line 86: | Line 81: | ||
= Links = | = Links = | ||
| − | This tool come from an altera [http://www.alteraforum.com/forum/showthread.php?t=35678 forum post], and the archive code can be found [ | + | This tool come from an altera [http://www.alteraforum.com/forum/showthread.php?t=35678 forum post], and the archive code can be found [https://github.com/Martoni/pcie_debug here]. |
Latest revision as of 15:23, 21 April 2021
Introduction
pci_debug is a useful tool meant to access PCIe BARx memory from userspace.
Buildroot configuration
- Should be done by default on APF6_SP
- Select pci_debug:
Target packages --->
Hardware handling --->
[*] pcidebug
- then rebuild your BSP:
$ make
Using pci_debug
- First find your PCI device name with lspci :
# lspci 00:00.0 PCI bridge: Device 16c3:abcd (rev 01) 01:00.0 Unclassified device [0013]: Altera Corporation Device e001 (rev 01)
For example here, we want to access Altera PCI device, then name is : 01:00.0
- Launch pci_debug with the BAR number in option (-b) :
# pci_debug -s 01:00.0 -b0
# ./pci_debug -s 01:00.0 -b0
PCI debug
---------
- accessing BAR0
- region size is 4194304-bytes
- offset into region is 0-bytes
? Help
d[width] addr len Display memory starting from addr
[width]
8 - 8-bit access
16 - 16-bit access
32 - 32-bit access (default)
c[width] addr val Change memory at addr to val
e Print the endian access mode
e[mode] Change the endian access mode
[mode]
b - big-endian (default)
l - little-endian
f[width] addr val len inc Fill memory
addr - start address
val - start value
len - length (in bytes)
inc - increment (defaults to 1)
q Quit
Notes:
1. addr, len, and val are interpreted as hex values
addresses are always byte based
PCI>
- You can then access BAR0 memory on PCI> prompt.
- Reading 0x20 values from address 0 :
PCI> d32 0 20 00000000: 12345678 12345678 12345678 12345678 00000010: 12345678 12345678 12345678 12345678 PCI>
Links
This tool come from an altera forum post, and the archive code can be found here.
