Difference between revisions of "APF6 SP DDR3 PINOUT"
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[[Category: FPGA]] | [[Category: FPGA]] | ||
[[Category: CycloneV]] | [[Category: CycloneV]] | ||
| + | |||
| + | == Introduction == | ||
| + | |||
| + | This page give pinout of CycloneV for [[APF6_SP]] project used on [[APF6_SP_Dev]]. | ||
== Button & Led == | == Button & Led == | ||
<source lang="tcl"> | <source lang="tcl"> | ||
| − | + | # HSMC_D2 -> PIN_L9 | |
| + | set_location_assignment PIN_L9 -to button | ||
| + | # HSMC_D0 -> PIN_M10 | ||
| + | set_location_assignment PIN_M10 -to led | ||
| + | </source> | ||
| + | |||
| + | == Random (not used) == | ||
| + | |||
| + | <source lang="tcl"> | ||
| + | |||
| + | # Random pinout (not used) | ||
| + | set_location_assignment PIN_Y16 -to drv_status_fail | ||
| + | set_location_assignment PIN_H18 -to drv_status_pass | ||
| + | set_location_assignment PIN_V18 -to drv_status_test_complete | ||
| + | set_location_assignment PIN_J17 -to local_cal_fail | ||
| + | set_location_assignment PIN_J19 -to local_cal_success | ||
| + | set_location_assignment PIN_AA7 -to local_init_done | ||
</source> | </source> | ||
| Line 26: | Line 46: | ||
# nperst | # nperst | ||
| − | set_location_assignment PIN_R17 -to | + | set_location_assignment PIN_R17 -to npor_pin_perst |
# npor | # npor | ||
| − | set_location_assignment PIN_R16 -to | + | set_location_assignment PIN_R16 -to npor_npor |
</source> | </source> | ||
| Line 50: | Line 70: | ||
set_location_assignment PIN_C8 -to memory_mem_a[12] | set_location_assignment PIN_C8 -to memory_mem_a[12] | ||
set_location_assignment PIN_B8 -to memory_mem_a[13] | set_location_assignment PIN_B8 -to memory_mem_a[13] | ||
| − | set_location_assignment PIN_H6 -to memory_mem_a[14] | + | #set_location_assignment PIN_H6 -to memory_mem_a[14] |
set_location_assignment PIN_C9 -to memory_mem_ba[2] | set_location_assignment PIN_C9 -to memory_mem_ba[2] | ||
| Line 107: | Line 127: | ||
set_location_assignment PIN_A12 -to oct_rzqin | set_location_assignment PIN_A12 -to oct_rzqin | ||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
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</source> | </source> | ||
Latest revision as of 10:55, 1 March 2016
Contents
Introduction
This page give pinout of CycloneV for APF6_SP project used on APF6_SP_Dev.
Button & Led
# HSMC_D2 -> PIN_L9
set_location_assignment PIN_L9 -to button
# HSMC_D0 -> PIN_M10
set_location_assignment PIN_M10 -to led
Random (not used)
# Random pinout (not used)
set_location_assignment PIN_Y16 -to drv_status_fail
set_location_assignment PIN_H18 -to drv_status_pass
set_location_assignment PIN_V18 -to drv_status_test_complete
set_location_assignment PIN_J17 -to local_cal_fail
set_location_assignment PIN_J19 -to local_cal_success
set_location_assignment PIN_AA7 -to local_init_done
PCIe
# PCIE_RX
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hip_serial_rx_in0
set_location_assignment PIN_AA2 -to hip_serial_rx_in0
set_location_assignment PIN_AA1 -to "hip_serial_rx_in0(n)"
# PCIE_TX
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hip_serial_tx_out0
set_location_assignment PIN_Y4 -to hip_serial_tx_out0
set_location_assignment PIN_Y3 -to "hip_serial_tx_out0(n)"
# PCIE_CLK
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to refclk_clk
set_location_assignment PIN_V4 -to refclk_clk
set_location_assignment PIN_U4 -to "refclk_clk(n)"
# nperst
set_location_assignment PIN_R17 -to npor_pin_perst
# npor
set_location_assignment PIN_R16 -to npor_npor
DDR3
Pinout placement
set_location_assignment PIN_C11 -to memory_mem_a[0]
set_location_assignment PIN_B11 -to memory_mem_a[1]
set_location_assignment PIN_A8 -to memory_mem_a[2]
set_location_assignment PIN_A7 -to memory_mem_a[3]
set_location_assignment PIN_D11 -to memory_mem_a[4]
set_location_assignment PIN_E11 -to memory_mem_a[5]
set_location_assignment PIN_F8 -to memory_mem_a[6]
set_location_assignment PIN_E7 -to memory_mem_a[7]
set_location_assignment PIN_D9 -to memory_mem_a[8]
set_location_assignment PIN_D8 -to memory_mem_a[9]
set_location_assignment PIN_B6 -to memory_mem_a[10]
set_location_assignment PIN_B5 -to memory_mem_a[11]
set_location_assignment PIN_C8 -to memory_mem_a[12]
set_location_assignment PIN_B8 -to memory_mem_a[13]
#set_location_assignment PIN_H6 -to memory_mem_a[14]
set_location_assignment PIN_C9 -to memory_mem_ba[2]
set_location_assignment PIN_C10 -to memory_mem_ba[1]
set_location_assignment PIN_C6 -to memory_mem_ba[0]
set_location_assignment PIN_A10 -to memory_mem_cas_n[0]
set_location_assignment PIN_J9 -to memory_mem_ck[0]
set_location_assignment PIN_J8 -to memory_mem_ck_n[0]
set_location_assignment PIN_H8 -to memory_mem_cs_n[0]
set_location_assignment PIN_C21 -to memory_mem_dm[2]
set_location_assignment PIN_C19 -to memory_mem_dm[1]
set_location_assignment PIN_A15 -to memory_mem_dm[0]
set_location_assignment PIN_C20 -to memory_mem_dq[23]
set_location_assignment PIN_B20 -to memory_mem_dq[22]
set_location_assignment PIN_D18 -to memory_mem_dq[21]
set_location_assignment PIN_E17 -to memory_mem_dq[20]
set_location_assignment PIN_A22 -to memory_mem_dq[19]
set_location_assignment PIN_A20 -to memory_mem_dq[18]
set_location_assignment PIN_E16 -to memory_mem_dq[17]
set_location_assignment PIN_D17 -to memory_mem_dq[16]
set_location_assignment PIN_C18 -to memory_mem_dq[15]
set_location_assignment PIN_B16 -to memory_mem_dq[14]
set_location_assignment PIN_C16 -to memory_mem_dq[13]
set_location_assignment PIN_C15 -to memory_mem_dq[12]
set_location_assignment PIN_A17 -to memory_mem_dq[11]
set_location_assignment PIN_B18 -to memory_mem_dq[10]
set_location_assignment PIN_F15 -to memory_mem_dq[9]
set_location_assignment PIN_E14 -to memory_mem_dq[8]
set_location_assignment PIN_A14 -to memory_mem_dq[7]
set_location_assignment PIN_C14 -to memory_mem_dq[6]
set_location_assignment PIN_D13 -to memory_mem_dq[5]
set_location_assignment PIN_C13 -to memory_mem_dq[4]
set_location_assignment PIN_B13 -to memory_mem_dq[3]
set_location_assignment PIN_B12 -to memory_mem_dq[2]
set_location_assignment PIN_E12 -to memory_mem_dq[1]
set_location_assignment PIN_F12 -to memory_mem_dq[0]
set_location_assignment PIN_G15 -to memory_mem_dqs[2]
set_location_assignment PIN_G14 -to memory_mem_dqs_n[2]
set_location_assignment PIN_G12 -to memory_mem_dqs[1]
set_location_assignment PIN_H12 -to memory_mem_dqs_n[1]
set_location_assignment PIN_H9 -to memory_mem_dqs[0]
set_location_assignment PIN_G8 -to memory_mem_dqs_n[0]
set_location_assignment PIN_A13 -to memory_mem_odt[0]
set_location_assignment PIN_B15 -to memory_mem_cke[0]
set_location_assignment PIN_A9 -to memory_mem_ras_n[0]
set_location_assignment PIN_E6 -to memory_mem_we_n[0]
set_location_assignment PIN_B22 -to memory_mem_reset_n
set_location_assignment PIN_A12 -to oct_rzqin
Technology pinout
set_instance_assignment -name IO_STANDARD "SSTL-135" -to oct_rzqin -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_dq[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dq[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dq[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_dq[1] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dq[1] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dq[1] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_dq[2] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dq[2] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dq[2] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_dq[3] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dq[3] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dq[3] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_dq[4] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dq[4] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dq[4] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_dq[5] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dq[5] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dq[5] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_dq[6] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dq[6] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dq[6] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_dq[7] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dq[7] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dq[7] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_dq[8] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dq[8] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dq[8] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_dq[9] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dq[9] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dq[9] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_dq[10] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dq[10] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dq[10] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_dq[11] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dq[11] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dq[11] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_dq[12] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dq[12] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dq[12] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_dq[13] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dq[13] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dq[13] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_dq[14] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dq[14] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dq[14] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_dq[15] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dq[15] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dq[15] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_dq[16] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dq[16] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dq[16] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_dq[17] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dq[17] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dq[17] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_dq[18] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dq[18] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dq[18] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_dq[19] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dq[19] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dq[19] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_dq[20] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dq[20] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dq[20] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_dq[21] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dq[21] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dq[21] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_dq[22] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dq[22] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dq[22] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_dq[23] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dq[23] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dq[23] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.35-V SSTL" -to memory_mem_dqs[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dqs[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dqs[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.35-V SSTL" -to memory_mem_dqs_n[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dqs_n[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dqs_n[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.35-V SSTL" -to memory_mem_dqs[1] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dqs[1] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dqs[1] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.35-V SSTL" -to memory_mem_dqs_n[1] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dqs_n[1] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dqs_n[1] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.35-V SSTL" -to memory_mem_dqs[2] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dqs[2] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dqs[2] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.35-V SSTL" -to memory_mem_dqs_n[2] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to memory_mem_dqs_n[2] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dqs_n[2] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.35-V SSTL" -to memory_mem_ck[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to memory_mem_ck[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.35-V SSTL" -to memory_mem_ck_n[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to memory_mem_ck_n[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_a[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to memory_mem_a[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_a[10] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to memory_mem_a[10] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_a[11] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to memory_mem_a[11] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_a[12] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to memory_mem_a[12] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_a[13] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to memory_mem_a[13] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_a[14] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to memory_mem_a[14] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_a[1] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to memory_mem_a[1] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_a[2] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to memory_mem_a[2] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_a[3] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to memory_mem_a[3] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_a[4] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to memory_mem_a[4] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_a[5] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to memory_mem_a[5] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_a[6] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to memory_mem_a[6] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_a[7] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to memory_mem_a[7] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_a[8] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to memory_mem_a[8] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_a[9] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to memory_mem_a[9] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_ba[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to memory_mem_ba[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_ba[1] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to memory_mem_ba[1] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_ba[2] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to memory_mem_ba[2] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_cas_n[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to memory_mem_cas_n[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_cke[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to memory_mem_cke[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_cs_n[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to memory_mem_cs_n[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_odt[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to memory_mem_odt[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_ras_n[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to memory_mem_ras_n[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_we_n[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to memory_mem_we_n[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_reset_n -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to memory_mem_reset_n -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_dm[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dm[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_dm[1] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dm[1] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to memory_mem_dm[2] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to memory_mem_dm[2] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to pll_ref_clk -tag __ddr3_contr_example_if0_p0
