Difference between revisions of "Using FPGA"

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* '''APF51''': [[IMX51-Spartan6 interface description]]
 
* '''APF51''': [[IMX51-Spartan6 interface description]]
 
* '''APF6_SP''': [[APF6_SP Interfaces description]]
 
* '''APF6_SP''': [[APF6_SP Interfaces description]]
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* '''OPOS6UL_SP''': [[OPOS6UL_SP Interfaces description]]
  
 
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'''Altera'''
 
'''Altera'''
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* [[Quartus | Quartus Web edition (Altera's free devt tool)]]
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* [[Quartus | Quartus Prime (Altera/Intel's free devt tool)]]
 
* [[Modelsim-Altera | Install Modelsim-Altera (starter edition)]]
 
* [[Modelsim-Altera | Install Modelsim-Altera (starter edition)]]
  
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* [[Diamond | Install Lattice Diamond]]
 
* [[Diamond | Install Lattice Diamond]]
  
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'''Microsemi'''
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* [http://www.fabienm.eu/flf/installing-libero-on-debian-9/ Install Libero]
  
 
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For complex projects, POD should be used to simplify design.
 
For complex projects, POD should be used to simplify design.
  
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==== [[Migen]] ====
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==== [[FuseSoC]] ====
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FuseSoC is a builder written in Python used to automatize FPGA constructions
  
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With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis.
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==== CactusII ====
  
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==== [[Chisel]] ====
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[http://funbase.cs.tut.fi/ Graphical IDE] for managing FPGA/ASIC design with IPX-ACT standard.
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With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthezis.
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=== HDL ===
  
 
===VHDL ===
 
===VHDL ===
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=== Verilog ===
 
=== Verilog ===
  
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* [https://www.veripool.org/wiki/verilator Verilator] an High speed verilog simulator
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* [http://iverilog.icarus.com/ Icarus] Famous open-source verilog simulator
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* [https://symbiyosys.readthedocs.io/en/latest/ SymbiYosys] open-source Verilog formal verification
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=== Synthesizable Synchronous HDL ===
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==== [[Migen]] ====
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With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis.
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 +
==== [[Chisel]] ====
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With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthesis. Armadeus system can help you to integrate a Chisel project on Armadeus board.
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==== [[SpinalHDL]] ====
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[https://github.com/SpinalHDL/SpinalHDL Another HDL generator] (VHDL) written in Scala.
  
 
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''' CycloneV'''
 
''' CycloneV'''
 
* [https://www.altera.com/products/fpga/cyclone-series/cyclone-v/overview.html CycloneV overview from altera]
 
* [https://www.altera.com/products/fpga/cyclone-series/cyclone-v/overview.html CycloneV overview from altera]
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''' OpenSource '''
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* [http://www.fabienm.eu/flf/wp-content/uploads/2017/05/fpgamap-1.svg OpenSource FPGA map]
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Latest revision as of 14:45, 12 November 2019


Developing on the APF FPGA

FPGA Interfaces

Using Armadeus FPGA

Manage the FPGA from Armadeus distribution.

Make some examples

These examples give the basis to make VHDL design for FPGA.



Design Tools

Description of tools used to simulate, to synthesize, and to download/configure FGPA.

Xilinx

Altera

Lattice

Microsemi

Automatize FPGA design making

Peripherals On Demand

For complex projects, POD should be used to simplify design.

FuseSoC

FuseSoC is a builder written in Python used to automatize FPGA constructions

CactusII

Graphical IDE for managing FPGA/ASIC design with IPX-ACT standard.

HDL

VHDL

Verilog

  • Verilator an High speed verilog simulator
  • Icarus Famous open-source verilog simulator
  • SymbiYosys open-source Verilog formal verification

Synthesizable Synchronous HDL

Migen

With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis.

Chisel

With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthesis. Armadeus system can help you to integrate a Chisel project on Armadeus board.

SpinalHDL

Another HDL generator (VHDL) written in Scala.

Links

Some useful links.

Wishbone

Spartan

CycloneV

OpenSource


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