Difference between revisions of "Using FPGA"
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'''Altera''' | '''Altera''' | ||
| − | * [[Quartus | Quartus | + | * [[Quartus | Quartus Prime (Altera/Intel's free devt tool)]] |
* [[Modelsim-Altera | Install Modelsim-Altera (starter edition)]] | * [[Modelsim-Altera | Install Modelsim-Altera (starter edition)]] | ||
| Line 58: | Line 58: | ||
* [[Diamond | Install Lattice Diamond]] | * [[Diamond | Install Lattice Diamond]] | ||
| + | '''Microsemi''' | ||
| + | * [http://www.fabienm.eu/flf/installing-libero-on-debian-9/ Install Libero] | ||
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For complex projects, POD should be used to simplify design. | For complex projects, POD should be used to simplify design. | ||
| − | ==== [[ | + | ==== [[FuseSoC]] ==== |
| + | FuseSoC is a builder written in Python used to automatize FPGA constructions | ||
| − | + | ==== CactusII ==== | |
| − | + | [http://funbase.cs.tut.fi/ Graphical IDE] for managing FPGA/ASIC design with IPX-ACT standard. | |
| − | + | ||
| width="50%" | | | width="50%" | | ||
| + | |||
| + | === HDL === | ||
===VHDL === | ===VHDL === | ||
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* [http://iverilog.icarus.com/ Icarus] Famous open-source verilog simulator | * [http://iverilog.icarus.com/ Icarus] Famous open-source verilog simulator | ||
* [https://symbiyosys.readthedocs.io/en/latest/ SymbiYosys] open-source Verilog formal verification | * [https://symbiyosys.readthedocs.io/en/latest/ SymbiYosys] open-source Verilog formal verification | ||
| + | |||
| + | === Synthesizable Synchronous HDL === | ||
| + | ==== [[Migen]] ==== | ||
| + | |||
| + | With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis. | ||
| + | |||
| + | ==== [[Chisel]] ==== | ||
| + | With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthesis. Armadeus system can help you to integrate a Chisel project on Armadeus board. | ||
| + | |||
| + | ==== [[SpinalHDL]] ==== | ||
| + | |||
| + | [https://github.com/SpinalHDL/SpinalHDL Another HDL generator] (VHDL) written in Scala. | ||
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''' CycloneV''' | ''' CycloneV''' | ||
* [https://www.altera.com/products/fpga/cyclone-series/cyclone-v/overview.html CycloneV overview from altera] | * [https://www.altera.com/products/fpga/cyclone-series/cyclone-v/overview.html CycloneV overview from altera] | ||
| + | |||
| + | ''' OpenSource ''' | ||
| + | |||
| + | * [http://www.fabienm.eu/flf/wp-content/uploads/2017/05/fpgamap-1.svg OpenSource FPGA map] | ||
| + | |||
| width="50%" | | | width="50%" | | ||
| + | |||
| + | |||
| + | |||
|} | |} | ||
Latest revision as of 14:45, 12 November 2019
Developing on the APF FPGA
FPGA Interfaces
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Using Armadeus FPGAManage the FPGA from Armadeus distribution.
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Make some examplesThese examples give the basis to make VHDL design for FPGA.
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Design ToolsDescription of tools used to simulate, to synthesize, and to download/configure FGPA. Xilinx Altera Lattice Microsemi |
Automatize FPGA design makingPeripherals On DemandFor complex projects, POD should be used to simplify design. FuseSoCFuseSoC is a builder written in Python used to automatize FPGA constructions CactusIIGraphical IDE for managing FPGA/ASIC design with IPX-ACT standard. |
HDLVHDL
Verilog
Synthesizable Synchronous HDLMigenWith migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis. ChiselWith Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthesis. Armadeus system can help you to integrate a Chisel project on Armadeus board. SpinalHDLAnother HDL generator (VHDL) written in Scala. |
LinksSome useful links. Wishbone Spartan CycloneV OpenSource |
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