Difference between revisions of "APF6 SP Interfaces description"
From ArmadeusWiki
(→Links) |
|||
| (One intermediate revision by the same user not shown) | |||
| Line 15: | Line 15: | ||
* [[IMX6-CycloneV interface description | IMX6-CycloneV interface description (PCIe)]] | * [[IMX6-CycloneV interface description | IMX6-CycloneV interface description (PCIe)]] | ||
| − | |||
* [[DDR3-CycloneV interface description | DDR3-CycloneV interface description]] | * [[DDR3-CycloneV interface description | DDR3-CycloneV interface description]] | ||
| + | * [[APF6_SP_DMA_simple_howto | APF6_SP_DMA_simple_howto]] | ||
= Pinouts = | = Pinouts = | ||
| Line 29: | Line 29: | ||
= Links = | = Links = | ||
| − | * [[Pci debug]]: a | + | * [[Pci debug]]: a tool for read/write in PCIe BAR. |
Latest revision as of 12:42, 5 July 2021
Introduction
This page describe the FPGA interfaces for APF6_SP.
Global schematic of FPGA under APF6_SP
i.MX6 to CycloneV
- IMX6-CycloneV interface description (PCIe)
- DDR3-CycloneV interface description
- APF6_SP_DMA_simple_howto
Pinouts
Howto
- The full FPGA howto for the APF6_sp, with PCIe, DDR3 and I/O
- Use JTaG USB-Blaster to access avalon bus memory on APF6_SP FPGA
Links
- Pci debug: a tool for read/write in PCIe BAR.
