Difference between revisions of "Using FPGA"

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== Introduction ==
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[[Category: FPGA]]
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[[FPGA | FPGA on APF introduction]]
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__NOTOC__
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==Developing on the APF FPGA==
 
==Developing on the APF FPGA==
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{| border="0" cellpadding="5" cellspacing="5" summary="Hardware Add-Ons by functionnalities" width="100%"
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{| border="0" cellpadding="5" cellspacing="5" summary="Hardware Add-Ons by functionalities" width="100%"
 
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|- style="background:#f4f4f4; color:black; -moz-border-radius:18px;"
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| width="50%" |
 
| width="50%" |
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===Tools===
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* [[InstallTargetSoftware#FPGA_firmware_installation|FPGA firmware installation]]
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=== FPGA Interfaces ===
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* [[ISE WebPack installation on Linux]]
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* [[How_to_make_a_VHDL_design_in_Ubuntu/Debian| How to setup the FPGA toolchain in Ubuntu/Debian]]
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* '''APF9328''': [[IMX9328-Spartan3 interface description]]
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* [[FPGA_loader | Configure FPGA from armadeus-Linux card]]
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* '''APF27''': [[IMX27-Spartan3A interface description]]
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* [[FPGA_register | read write on fpga address domain from linux]]
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* '''APF51''': [[IMX51-Spartan6 interface description]]
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* [[How to simulate post synthesis and post place & route design with GHDL]]
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* '''APF6_SP''': [[APF6_SP Interfaces description]]
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* '''OPOS6UL_SP''': [[OPOS6UL_SP Interfaces description]]
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| width="50%" |
  
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===Xilinx documentation links===
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===Using Armadeus FPGA===
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* [http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf Spartan-3 FPGA Family Data Sheet]
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Manage the FPGA from Armadeus distribution.
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* Configure the FPGA [[FPGA_loader | from Linux]], [[Target_Software_Installation#FPGA_firmware_test | from U-Boot]], [[PCIe_fpga_load | from PCIe]].
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* Flashing FPGA firmware [[Uboot_FPGA_firmware_update_from_Linux | from Linux]], [[Target_Software_Installation#FPGA_firmware_installation | from U-Boot]]
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* [[FPGA_register | Access the FPGA address domain from Linux]]
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=== Make some examples ===
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These examples give the basis to make VHDL design for FPGA.
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* [[Simple blinking LED | LED]]
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* [[A simple design with Wishbone bus | Complete example with button and led on wishbone bus communication and Linux drivers]]
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| width="50%" |
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===Designs===
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* [[FPGA and led]]
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=== Design Tools===
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* [[A simple design with Wishbone bus]]
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Description of tools used to simulate, to synthesize, and to download/configure FGPA.
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* [[Une led qui clignote avec le spartan 3 ]](French)
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*
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'''Xilinx'''
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* [http://www.xess.com/ho03000.html Nice ideas/examples to look at]
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* [[ISE WebPack and Vivado]]
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'''Altera'''
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* [[Quartus | Quartus Prime (Altera/Intel's free devt tool)]]
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* [[Modelsim-Altera | Install Modelsim-Altera (starter edition)]]
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'''Lattice'''
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* [[IceCube | Install IceCube]]
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* [[Diamond | Install Lattice Diamond]]
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'''Microsemi'''
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* [http://www.fabienm.eu/flf/installing-libero-on-debian-9/ Install Libero]
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===Links VHDL===
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=== Automatize FPGA design making ===
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==== [[Peripherals On Demand]] ====
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For complex projects, POD should be used to simplify design.
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 +
==== [[FuseSoC]] ====
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FuseSoC is a builder written in Python used to automatize FPGA constructions
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 +
==== CactusII ====
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[http://funbase.cs.tut.fi/ Graphical IDE] for managing FPGA/ASIC design with IPX-ACT standard.
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| width="50%" |
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=== HDL ===
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===VHDL ===
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* [[VHDL coding styles|VHDL coding styles & externals documentations]]
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* [http://www.xess.com/design_examples.php#XESS_Examples Nice ideas/examples to look at]
 
* [http://www.opencores.org www.opencores.org]
 
* [http://www.opencores.org www.opencores.org]
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* [http://www.chez.com/amouf/syntaxe.htm Syntaxe VHDL (French)]
 
 
* [http://www.gmvhdl.com/VHDL.html An Introductory VHDL Tutorial]
 
* [http://www.gmvhdl.com/VHDL.html An Introductory VHDL Tutorial]
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* [http://www.xess.com/ho03000.html Nice ideas/examples to look at]
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=== Verilog ===
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* [https://www.veripool.org/wiki/verilator Verilator] an High speed verilog simulator
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* [http://iverilog.icarus.com/ Icarus] Famous open-source verilog simulator
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* [https://symbiyosys.readthedocs.io/en/latest/ SymbiYosys] open-source Verilog formal verification
 +
 
 +
=== Synthesizable Synchronous HDL ===
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==== [[Migen]] ====
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With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis.
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 +
==== [[Chisel]] ====
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With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthesis. Armadeus system can help you to integrate a Chisel project on Armadeus board.
 +
 
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==== [[SpinalHDL]] ====
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[https://github.com/SpinalHDL/SpinalHDL Another HDL generator] (VHDL) written in Scala.
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===Orchestra===
 
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* [[Orchestra | Spécification d'Orchestra (French)]]
 
  
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----
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===Links===
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''Draft:''
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Some useful links.
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* [[Usecases | Diagrammes des cas d'utilisations du logiciel]]
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* [[OrchestraPython | Elaboration du projet Orchestra en Python (French)]]
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* [[FpgaArchitecture | Spécification de l'architecture du FPGA (french)]]
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| width="50%" |
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''' Wishbone '''
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===Links Orchestra===
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* [http://cdn.opencores.org/downloads/wbspec_b3.pdf  official Wishbone specifications]
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* [http://www.opencores.org/projects.cgi/web/wishbone/wbspec_b3.pdf  official Wishbone specifications]
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* [http://en.wikipedia.org/wiki/Wishbone_%28computer_bus%29 Wikipedia Wishbone doc]
 
* [http://en.wikipedia.org/wiki/Wishbone_%28computer_bus%29 Wikipedia Wishbone doc]
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|----------------
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''' Spartan '''
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* [http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf Spartan-3 FPGA Family Data Sheet]
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''' CycloneV'''
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* [https://www.altera.com/products/fpga/cyclone-series/cyclone-v/overview.html CycloneV overview from altera]
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''' OpenSource '''
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* [http://www.fabienm.eu/flf/wp-content/uploads/2017/05/fpgamap-1.svg OpenSource FPGA map]
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| width="50%" |
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Latest revision as of 14:45, 12 November 2019


Developing on the APF FPGA

FPGA Interfaces

Using Armadeus FPGA

Manage the FPGA from Armadeus distribution.

Make some examples

These examples give the basis to make VHDL design for FPGA.



Design Tools

Description of tools used to simulate, to synthesize, and to download/configure FGPA.

Xilinx

Altera

Lattice

Microsemi

Automatize FPGA design making

Peripherals On Demand

For complex projects, POD should be used to simplify design.

FuseSoC

FuseSoC is a builder written in Python used to automatize FPGA constructions

CactusII

Graphical IDE for managing FPGA/ASIC design with IPX-ACT standard.

HDL

VHDL

Verilog

  • Verilator an High speed verilog simulator
  • Icarus Famous open-source verilog simulator
  • SymbiYosys open-source Verilog formal verification

Synthesizable Synchronous HDL

Migen

With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis.

Chisel

With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verilog model for synthesis. Armadeus system can help you to integrate a Chisel project on Armadeus board.

SpinalHDL

Another HDL generator (VHDL) written in Scala.

Links

Some useful links.

Wishbone

Spartan

CycloneV

OpenSource


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