Difference between revisions of "IR Receiver"
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RC5 IP in the FPGA will decode Manchester frames and store them in a FIFO. At that time it will generate an interrupt to signal i.MXL Linux driver that data are available. | RC5 IP in the FPGA will decode Manchester frames and store them in a FIFO. At that time it will generate an interrupt to signal i.MXL Linux driver that data are available. | ||
| − | IP will be configurable with: | + | This IP will conform to Wishbone/POD interface and be configurable with: |
| − | * a | + | * a control register to activate/deactivate interrupt |
| − | * a status register to see interrupt status and acknowledge them | + | {| border="0" cellpadding="5" cellspacing="0" summary="IR CTRL" |
| − | * a FIFO register to get RC5 frame one at a time (and prevent frame lost when one is currently being received) | + | |- style="background:#efefef;" |
| + | |---------------- | ||
| + | | '''IR_CTRL''' || colspan="13" align="center" | IR IP Control Register || colspan="3" align="right" | '''Addr 0x0000''' | ||
| + | |---------------- align="center" | ||
| + | | BIT || 15 || 14 || 13 || 12 || 11 || 10 || 9 || 8 || 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 | ||
| + | |---------------- align="center" | ||
| + | | || style="border:1px solid black;" | -- || style="border:1px solid black;" | -- || style="border:1px solid black;" | -- || style="border:1px solid black;" | -- || style="border:1px solid black;" | -- || style="border:1px solid black;" | -- || style="border:1px solid black;" | -- || style="border:1px solid black;" | -- || style="border:1px solid black;" | -- || style="border:1px solid black;" | -- || style="border:1px solid black;" | -- || style="border:1px solid black;" | -- || style="border:1px solid black;" | -- || style="border:1px solid black;" | -- || style="border:1px solid black;" | -- || style="border:1px solid black;" | IT_EN | ||
| + | |---------------- align="center" | ||
| + | | TYPE || r || r || r || r || r || r || r || r || r || r || r || r || r || r || r || rw | ||
| + | |---------------- align="center" | ||
| + | | rowspan="2" | RESET || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 | ||
| + | |---------------- | ||
| + | | colspan="17" align="center" | 0x0000 | ||
| + | |- | ||
| + | |} | ||
| + | |||
| + | * a status register to see interrupt status and acknowledge them: will use wishbone irq_handler | ||
| + | * a FIFO register to get RC5 frame one at a time (and prevent frame lost when one is currently being received): | ||
| + | {| border="0" cellpadding="5" cellspacing="0" summary="IR FIFO" | ||
| + | |- style="background:#efefef;" | ||
| + | |---------------- | ||
| + | | '''IR_FIFO''' || colspan="13" align="center" | IR FIFO Register || colspan="3" align="right" | '''Addr 0x0000''' | ||
| + | |---------------- align="center" | ||
| + | | BIT || 15 || 14 || 13 || 12 || 11 || 10 || 9 || 8 || 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 | ||
| + | |---------------- align="center" | ||
| + | | || colspan="16" style="border:1px solid black;" | FIFO_VALUE[15:0] | ||
| + | |---------------- align="center" | ||
| + | | TYPE || r || r || r || r || r || r || r || r || r || r || r || r || r || r || r || rw | ||
| + | |---------------- align="center" | ||
| + | | rowspan="2" | RESET || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 | ||
| + | |---------------- | ||
| + | | colspan="17" align="center" | 0x0000 | ||
| + | |- | ||
| + | |} | ||
==Software== | ==Software== | ||
Latest revision as of 19:02, 29 October 2008
This page will summarize the informations to connect an InfraRed receiver to your Armadeus board
Contents
Introduction
Most IR remote control send their key code using the RC5 protocol (see links). This protocol can be mostly seen as a one wire serial Manchester link. In this application we will see how to user 38Khz carrier IR receiver.
Hardware
For our first tries we choose the Sharp's xxxxx IR receiver. This chip is 3,3v compatible and can be directly connected to i.MXL or FPGA IOs.
As RC5 decoding in software is quite a big overhead, we choose to implement an RC5 decoding IP for the FPGA.
On x86 architecture a serial port is often used to decode RC5 frames but it's very CPU consuming.
RC5 IP in the FPGA will decode Manchester frames and store them in a FIFO. At that time it will generate an interrupt to signal i.MXL Linux driver that data are available.
This IP will conform to Wishbone/POD interface and be configurable with:
- a control register to activate/deactivate interrupt
| IR_CTRL | IR IP Control Register | Addr 0x0000 | ||||||||||||||
| BIT | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | IT_EN | |
| TYPE | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | rw |
| RESET | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0x0000 | ||||||||||||||||
- a status register to see interrupt status and acknowledge them: will use wishbone irq_handler
- a FIFO register to get RC5 frame one at a time (and prevent frame lost when one is currently being received):
| IR_FIFO | IR FIFO Register | Addr 0x0000 | ||||||||||||||
| BIT | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FIFO_VALUE[15:0] | ||||||||||||||||
| TYPE | r | r | r | r | r | r | r | r | r | r | r | r | r | r | r | rw |
| RESET | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0x0000 | ||||||||||||||||
Software
We will use LIRC framework. A custom Linux driver will have to be written. As RC5 is very similar to PS/2 we will reuse the work done for PS/2 controller.
