Difference between revisions of "APF51 FPGA-IMX interface description"
From ArmadeusWiki
(→Hardware) |
(→Hardware) |
||
| (7 intermediate revisions by 2 users not shown) | |||
| Line 1: | Line 1: | ||
{{Under_Construction}} | {{Under_Construction}} | ||
| − | This article describe the interface between | + | This article describe the interface between the i.MX51 and the Spartan6 on [[APF51]]. |
| − | Documentation of i.MX interface can be found in the | + | Documentation of i.MX interface can be found in the i.MX reference manual, chapter 63, «Wireless External Interface Module ('''WEIM''')». |
| − | «Wireless External Interface Module ('''WEIM''')». | + | |
== Hardware == | == Hardware == | ||
| − | The detailed electronic schematics of | + | The detailed electronic schematics of [[APF51]] FPGA interface can be found on [http://www.armadeus.com/_downloads/apf51/hardware/apf51.pdf this document] page 15. |
| − | [http://www.armadeus.com/_downloads/apf51/hardware/apf51.pdf this document] page 15. | + | |
Signals used in the design are: | Signals used in the design are: | ||
* '''BCLK''': bus clock. | * '''BCLK''': bus clock. | ||
| − | * '''EB[2]''': | + | * '''EB[2]''': Those active-low output signals indicate active data bytes for the current access. They may be configured to assert for write cycles only. |
| − | * ''' | + | * '''CS2''': Chip select 1 corresponding to address B800_0000 |
| − | * '''CS1''': | + | * '''CS1''': Chip select 2 corresponding to address C000_0000 |
* '''LBA''': Noted ''ADV'' in reference manual. | * '''LBA''': Noted ''ADV'' in reference manual. | ||
* '''DA[16]''': Address/Data multiplexed bus. | * '''DA[16]''': Address/Data multiplexed bus. | ||
* '''CLK0''': General clock for FPGA, generated by the i.MX51 | * '''CLK0''': General clock for FPGA, generated by the i.MX51 | ||
* '''OE''': Read signal | * '''OE''': Read signal | ||
| − | * '''RW''': Write signal | + | * '''RW''': Read/Write signal |
| − | * '''DTACK''': | + | * '''DTACK''': used as a data ack. signal for single async. accesses. |
| − | * '''WAIT''': | + | * '''WAIT''': For burst mode, asserted when slave is busy. |
| − | + | ||
| − | + | ||
| − | + | ||
| − | + | ||
| − | + | ||
Latest revision as of 17:37, 15 March 2011
Page under construction...
Informations on this page are not guaranteed !!
This article describe the interface between the i.MX51 and the Spartan6 on APF51. Documentation of i.MX interface can be found in the i.MX reference manual, chapter 63, «Wireless External Interface Module (WEIM)».
Hardware
The detailed electronic schematics of APF51 FPGA interface can be found on this document page 15.
Signals used in the design are:
- BCLK: bus clock.
- EB[2]: Those active-low output signals indicate active data bytes for the current access. They may be configured to assert for write cycles only.
- CS2: Chip select 1 corresponding to address B800_0000
- CS1: Chip select 2 corresponding to address C000_0000
- LBA: Noted ADV in reference manual.
- DA[16]: Address/Data multiplexed bus.
- CLK0: General clock for FPGA, generated by the i.MX51
- OE: Read signal
- RW: Read/Write signal
- DTACK: used as a data ack. signal for single async. accesses.
- WAIT: For burst mode, asserted when slave is busy.
