Difference between revisions of "IMX51-Spartan6 interface description"
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| − | This article describe the bus interface configuration to communicate between i.MX51 processor and Spartan6 FPGA. | + | == Introduction == |
| + | This article describe the bus interface configuration to communicate between i.MX51 processor and Spartan6 FPGA. In i.MX51, the bus used to make communication with the FPGA is named '''WEIM''' for Wireless Extension Interface Module. All description of this bus can be found under the [http://cache.freescale.com/files/dsp/doc/ref_manual/MCIMX51RM.pdf?fpsp=1&WT_TYPE=Reference%20Manuals&WT_VENDOR=FREESCALE&WT_FILE_FORMAT=pdf&WT_ASSET=Documentation i.MX51 reference manual] in chapter 63 (page 3113). | ||
== Simplified view == | == Simplified view == | ||
Revision as of 14:32, 13 January 2012
Introduction
This article describe the bus interface configuration to communicate between i.MX51 processor and Spartan6 FPGA. In i.MX51, the bus used to make communication with the FPGA is named WEIM for Wireless Extension Interface Module. All description of this bus can be found under the i.MX51 reference manual in chapter 63 (page 3113).
Simplified view
Figure 1 is a simplified view of APF51 schematics (page 15), signals are :
- BCLK: i.MX51 bulk clock used to clock the spartan6.
- DA[15:0] : Data/Address multiplexed bus.
- LBA : Noted ADV for ADdress Valid under the i.MX51 reference manual.
- EB0, EB1 : For Enable Byte, write signal for lower byte and upper byte on data bus.
- CS1 : Chip Select 1.
- CS2 : Chip Select 2.
- OE : For Output Enable bit, read signal. (Motorola way of bus)
- RW : Read/Write signal. (Intel way of bus)
- DTACK : Data acknoledge, for asynchronous access.
- WAIT : Wait signal used for some burst access.
Not part of WEIM bus :
- CLK0 : An i.MX51 output clock (not used ).
- FPGA_INITB : used by default for interrupts (GPIO4_11).
Signals in bold are signals used in default configuration.
