Difference between revisions of "Using FPGA"
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With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis. | With migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis. | ||
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+ | With Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verliog model for synthezis. | ||
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Revision as of 10:02, 4 December 2015
Developing on the APF FPGA
1. Starting Up with FPGAAll you need to know to play with the Armadeus FPGA.
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Design ToolsDescription of tools used to simulate, to synthesize, and to download/configure FGPA. Xilinx
Altera |
2. Make some examplesThese examples give the basis to make VHDL design for FPGA.
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Using Armadeus FPGAManage the FPGA from Armadeus distribution.
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3. Automatize FPGA design makingPeripherals On DemandFor complex projects, POD should be used to simplify design. MigenWith migen, it's possible to develop FPGA design in Python then generate Verilog for synthezis.
ChiselWith Chisel, it's possible to develop FPGA design in Scala then generate C++ model for simulation and Verliog model for synthezis. |
VHDL
Verilog |
FPGA Interfaces
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LinksSome useful links. Wishbone Spartan CycloneV |