Difference between revisions of "Chisel"
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This module is used to do the Wishbone plumbing across different wishbones master and slave modules. It can generate Intercon as described in the [https://www.librecores.org/fossi-foundation/wishbone wishbone documentation]. | This module is used to do the Wishbone plumbing across different wishbones master and slave modules. It can generate Intercon as described in the [https://www.librecores.org/fossi-foundation/wishbone wishbone documentation]. | ||
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== spi2wb == | == spi2wb == | ||
Revision as of 13:20, 3 October 2019
Introduction
Introduction from the official website.
Chisel is a hardware design language that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs. Chisel adds hardware construction primitives to the Scala programming language, providing designers with the power of a modern programming language to write complex, parametrizable circuit generators that produce synthesizable Verilog. This generator methodology enables the creation of re-usable components and libraries, such as the FIFO queue and arbiters in the Chisel Standard Library, raising the level of abstraction in design while retaining fine-grained control.
Chisel is used in some internal Armadeus project. This page list some opensourced chisel components written by Armadeus.
Armadeus Library
All chisel modules presented here are wrote in Chisel3 and must be "published localy" to be used.
WbPlumbing
This module is used to do the Wishbone plumbing across different wishbones master and slave modules. It can generate Intercon as described in the wishbone documentation.
spi2wb
spi2wb is a Wisbone master driven by SPI. It permit read/write under a design with a simple spi master.
MDIO
MDIO is a Wishbone slave used to write frames on phy mdio bus.
