Difference between revisions of "A simple design with Wishbone bus"

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m (→‎Wb_led)
m (→‎Wb_button)
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[[Image:wbs_button.png|center|500px]]
 
[[Image:wbs_button.png|center|500px]]
  
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The VHDL source code is:
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[[Wb_button.vhd | The VHDL source c]]ode
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<source lang="VHDL">
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.all;
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---------------------------------------------------------------------------
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Entity Wb_button is
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---------------------------------------------------------------------------
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port
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(
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-- global signals
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wbc_candr_reset : in std_logic ;
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wbc_candr_clk : in std_logic ;
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-- Wishbone signals
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wbs_sbutton_readdata  : out std_logic_vector( 15 downto 0);
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wbs_sbutton_strobe    : in std_logic ;
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wbs_sbutton_write   : in std_logic ;
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wbs_sbutton_ack       : out std_logic;
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-- irq
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wbs_sbutton_irq : out std_logic ;
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-- fpga input
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gls_button_export : in std_logic
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);
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end entity;
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---------------------------------------------------------------------------
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Architecture Wb_button_1 of Wb_button is
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---------------------------------------------------------------------------
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signal button_r : std_logic ;
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signal reg : std_logic_vector( 15 downto 0);
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begin
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-- connect button
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cbutton : process(wbc_candr_clk,wbc_candr_reset)
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begin
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if wbc_candr_reset = '1' then
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reg <= (others => '0');
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elsif rising_edge(wbc_candr_clk) then
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reg <= "000000000000000"&gls_button_export;
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end if;
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end process cbutton;
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-- rise interruption
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pbutton : process(wbc_candr_clk,wbc_candr_reset)
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begin
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if wbc_candr_reset = '1' then
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wbs_sbutton_irq <= '0';
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button_r <= '0';
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elsif rising_edge(wbc_candr_clk) then
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if button_r /= gls_button_export then
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wbs_sbutton_irq <= '1';
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else
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wbs_sbutton_irq <= '0';
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end if;
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button_r <= gls_button_export;
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end if;
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end process pbutton;
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-- register reading process
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pread : process(wbc_candr_clk,wbc_candr_reset)
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begin
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if(wbc_candr_reset = '1') then
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wbs_sbutton_ack <= '0';
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wbs_sbutton_readdata <= (others => '0');
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elsif(falling_edge(wbc_candr_clk)) then
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wbs_sbutton_ack <= '1';
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if(wbs_sbutton_strobe = '1' and wbs_sbutton_write = '0')then
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wbs_sbutton_readdata <= reg;
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end if;
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end if;
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end process pread;
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end architecture Wb_button_1;
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</source>
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== Drivers ==
 
== Drivers ==
  
 
== XML ==
 
== XML ==

Revision as of 15:16, 31 March 2008

This article intended to explain how to design Wishbone compatible components with simple example. The design can be found in sourceforge tree.

Description of wishbone structure for armadeus can be found here in french.

General structure

The main functionality of this component is to do the same things that benoît project : switch on a led when a button is pressed.

But to learn about designing Wishbone component and linux driver, the design is little bit more complicated (!).

When button is pressed, the component Wb_button send interrupt signal to irq_mngr. irq_mngr will toggle a flag and send interruption to i.mx processor. A Linux driver on i.mx will read irq_mngr and acknowledge irq by writing '1' on a register. And finally, Linux driver will toggle led value by writing on led register.


Wb buttonled top.png


imx_wrapper, syscon and irq_mngr are standards ARMadeus-Wishbone IPs that just been instantiated in our design.

Wb_button and Wb_led are simple slave component we want to integrate in the FPGA.

All these components are connected together with the 'glue logic' component intercon.

Wishbone slave application components

Wb_led

This component is a simple 16-bit Wishbone slave output port, from wishbone specification example (p110).

Wbs led.png

It is a simple register, that can be read and write. The led is controled with register pin 0.

The VHDL source code

Wb_button

Wb_button component, is like Wb_led but in read only and with an edge detector to rise irq.

Wbs button.png

The VHDL source code

Drivers

XML

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