Difference between revisions of "A simple design with Wishbone bus"

Revision as of 10:49, 3 March 2009

This article intended to explain how to design Wishbone compatible components with simple example. The VHDL code sources can be found in sourceforge tree.

Description of wishbone structure for armadeus can be found here in french.

General structure

The main functionality of this component is to do the same things that benoît project : switch on a led when a button is pressed.

But to learn about designing Wishbone component and linux driver, the design is little bit more complicated (!).

When button is pressed, the component Wb_button send interrupt signal to irq_mngr. irq_mngr will toggle a flag and send interruption to i.mx processor. A Linux driver on i.mx will read irq_mngr and acknowledge irq by writing '1' on a register. And finally, Linux driver will toggle led value by writing on led register.

imx_wrapper, syscon and irq_mngr are standards ARMadeus-Wishbone IPs that just been instantiated in our design.

Wb_button and Wb_led are simple slave component we want to integrate in the FPGA.

All these components are connected together with the 'glue logic' component intercon.

Wrapper

Wrapper is used to convert i.MX interface signals into Wishbone signals.

intercon

The intercon is a component used to manage signal between wishbone master and slaves component.

Wishbone slave application components

irq manager

Some component generate interrupts, irq manager is used to group these interrupts and generate one for i.MX.

wb_led

This component is a simple 16-bit Wishbone slave output port, from wishbone specification example (p110).

It is a simple register, that can be read and write. The led is controled with register pin 0.

wb_button

Wb_button component, is like Wb_led but in read only and with an edge detector to rise irq.