Difference between revisions of "APF51"
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* [[PWM]]: PWM output J2 pin 18 (2.8V output level if used) | * [[PWM]]: PWM output J2 pin 18 (2.8V output level if used) | ||
* [[GPIO_Driver]] | * [[GPIO_Driver]] | ||
| + | * [[APF51_PMIC]] | ||
===FPGA=== | ===FPGA=== | ||
* [[Using_FPGA]] | * [[Using_FPGA]] | ||
Revision as of 16:45, 4 May 2011
Contents
Description
The APF51 is a high-end Single Board Computer targeted for advanced GUI, intensive computation and extended connectivity.
Here is a list of the main features:
- Processor: Freescale i.MX51 (Cortex-A8 @ 800MHz)
- RAM: Mobile DDR 400. 64 to 512MB. 32 bits data bus. Default capacity will be 256MB.
- Flash: Mobile NAND. 512MB, 8 bits data bus.
- Ethernet: onboard Physical (ready to use Ethernet 10/100Mbit link)
- USB: High speed USB OTG (OnTheGo) with onboard Physical (ready to use USB OTG link)
- USB: 2 High speed Hosts with integrated PHY
- FPGA: Xilinx Spartan 6 (LX9 or LX16). Default: LX9
- Touchscreen controler (4/5 wires)
- Low speed ADCs (up to 4)
- RTC and Watchdog
- Battery charger (Li-On/Li-Po)
- Supplies: high end DC/DC converters and LDOs on board. Only one external supply of 5V required.
- Low power sleep mode
- Mechanical dimensions: ~00x00mm (TBD)
All the i.MX51 peripherals (LCD, 2xSDIO, 2xSPI, 6xSerial, I2C, CSI, 3xUSB, keypad, PWM, etc...) and the FPGA signals can be accessed through two high density Hirose connectors.
Resources
- TBD
Feature list
VideoVideo OutVideo In |
Wired communicationUser Input |
StorageOther
FPGA |
