Difference between revisions of "IMX51-Spartan6 interface description"
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[[image:Imx51-spartan6.jpg|700px|center|thumb|'''figure 1''' - ''i.MX51-Spartan6 bus description'']] | [[image:Imx51-spartan6.jpg|700px|center|thumb|'''figure 1''' - ''i.MX51-Spartan6 bus description'']] | ||
| − | Figure 1 is a simplified view of [[Datasheet#APF51 | APF51 schematics]] (page 15) : | + | Figure 1 is a simplified view of [[Datasheet#APF51 | APF51 schematics]] (page 15), signals are : |
Revision as of 11:09, 13 January 2012
This article describe the bus interface configuration to communicate between i.MX51 processor and Spartan6 FPGA.
Figure 1 is a simplified view of APF51 schematics (page 15), signals are :
