Difference between revisions of "IMX51-Spartan6 interface description"
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This article describe the bus interface configuration to communicate between i.MX51 processor and Spartan6 FPGA. | This article describe the bus interface configuration to communicate between i.MX51 processor and Spartan6 FPGA. | ||
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| + | == Simplified view == | ||
[[image:Imx51-spartan6.jpg|700px|center|thumb|'''figure 1''' - ''i.MX51-Spartan6 bus description'']] | [[image:Imx51-spartan6.jpg|700px|center|thumb|'''figure 1''' - ''i.MX51-Spartan6 bus description'']] | ||
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Figure 1 is a simplified view of [[Datasheet#APF51 | APF51 schematics]] (page 15), signals are : | Figure 1 is a simplified view of [[Datasheet#APF51 | APF51 schematics]] (page 15), signals are : | ||
| − | * BCLK: i.MX51 bulk clock used to clock the spartan6. | + | * '''BCLK''': i.MX51 bulk clock used to clock the spartan6. |
| − | * DA[15:0] : Data/Address multiplexed bus. | + | * '''DA'''[15:0] : Data/Address multiplexed bus. |
| − | * LBA : Noted ADV | + | * '''LBA''' : Noted '''ADV''' for ''AD''dress ''V''alid under the i.MX51 reference manual. |
* EB0, EB1 : For Enable Byte, write signal for lower byte and upper byte on data bus. | * EB0, EB1 : For Enable Byte, write signal for lower byte and upper byte on data bus. | ||
* CS1 : Chip Select 1. | * CS1 : Chip Select 1. | ||
* CS2 : Chip Select 2. | * CS2 : Chip Select 2. | ||
* OE : For Output Enable bit, read signal. (Motorola way of bus) | * OE : For Output Enable bit, read signal. (Motorola way of bus) | ||
| − | * RW : Read/Write signal. (Intel way of bus) | + | * '''RW''' : Read/Write signal. (Intel way of bus) |
* DTACK : Data acknoledge, for asynchronous access. | * DTACK : Data acknoledge, for asynchronous access. | ||
* WAIT : Wait signal used for some burst access. | * WAIT : Wait signal used for some burst access. | ||
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* CLK0 : An i.MX51 output clock (not used ). | * CLK0 : An i.MX51 output clock (not used ). | ||
* FPGA_INITB : used by default for interrupts (GPIO4_11). | * FPGA_INITB : used by default for interrupts (GPIO4_11). | ||
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| + | Signals in '''bold''' are signals used in default configuration. | ||
| + | |||
| + | == Default configuration == | ||
Revision as of 14:26, 13 January 2012
This article describe the bus interface configuration to communicate between i.MX51 processor and Spartan6 FPGA.
Simplified view
Figure 1 is a simplified view of APF51 schematics (page 15), signals are :
- BCLK: i.MX51 bulk clock used to clock the spartan6.
- DA[15:0] : Data/Address multiplexed bus.
- LBA : Noted ADV for ADdress Valid under the i.MX51 reference manual.
- EB0, EB1 : For Enable Byte, write signal for lower byte and upper byte on data bus.
- CS1 : Chip Select 1.
- CS2 : Chip Select 2.
- OE : For Output Enable bit, read signal. (Motorola way of bus)
- RW : Read/Write signal. (Intel way of bus)
- DTACK : Data acknoledge, for asynchronous access.
- WAIT : Wait signal used for some burst access.
Not part of WEIM bus :
- CLK0 : An i.MX51 output clock (not used ).
- FPGA_INITB : used by default for interrupts (GPIO4_11).
Signals in bold are signals used in default configuration.
