Difference between revisions of "IMX9328-Spartan3 interface description"
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This article describes the bus interface configuration to communicate between the i.MX9328 processor and the Spartan3 FPGA of the APF9328 board. | This article describes the bus interface configuration to communicate between the i.MX9328 processor and the Spartan3 FPGA of the APF9328 board. | ||
Latest revision as of 08:34, 12 February 2015
Page under construction...
Informations on this page are not guaranteed !!
This article describes the bus interface configuration to communicate between the i.MX9328 processor and the Spartan3 FPGA of the APF9328 board.
Default configuration on CS1n
CS1n is accessed via the address 0x1200 0000.
Clock
The clock used to clock the fpga is configured to 96 MHz.
