Difference between revisions of "Migen"
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* [http://m-labs.hk/gateware.html Official migen presentation] | * [http://m-labs.hk/gateware.html Official migen presentation] | ||
* [http://connect.ed-diamond.com/GNU-Linux-Magazine/GLMF-149/Migen-une-boite-a-outils-en-Python-pour-concevoir-des-circuits-logiques-complexes An article in GLMF 149 (french Linux Magazine)] | * [http://connect.ed-diamond.com/GNU-Linux-Magazine/GLMF-149/Migen-une-boite-a-outils-en-Python-pour-concevoir-des-circuits-logiques-complexes An article in GLMF 149 (french Linux Magazine)] | ||
| − | * [http://www. | + | * [http://www.fabienm.eu/flf/experimentations-de-migen-sur-apf27-avec-debian/ Some experiments for APF27 (fr)] |
Revision as of 15:00, 22 March 2016
Contents
Introduction
Migen is a Python module that makes FPGA design possible without VHDL or Verilog. Writing a Migen design for FPGA is like writing Python program. If it's correctly configured with ISE or Quartus, Migen is also capable of generating the bitstream directly.
APF27 and APF51 platforms have been integrated under Migen in July 2014, so designs can be done with it for these APF.
Installing Migen
Requirements
- Python 3.4 minimum
- git
- python setuptools: to use in developpement python module
# On debian: sudo apt-get install python-setuptools
- ISE webpack: to generate bitstream for apf27, apf51
- Quartus web edition: to generate bitstream for apf6sp
installation
Migen is an under developpement python3 module. To install it python 3.4 is required.
- first download the git tree:
$ git clone https://github.com/m-labs/migen.git
- Then install it as developpement module:
$ cd migen $ sudo python setup.py develop
- To be up-to-date with the github tree, do not forget to pull fresh version regularly :
$ cd migen $ git pull
Blink LED example
APF27
#!/usr/local/bin/python3.4
# -*- coding: utf-8 -*-
from migen import *
from migen.fhdl import *
from migen.build.generic_platform import Pins, IOStandard
from migen.build.platforms import apf27
ios = [
("user_led", 0, Pins("J2:22"), IOStandard("LVCMOS33"))
]
plat = apf27.Platform()
plat.add_extension(ios)
led = plat.request("user_led", 0) # led pin on apf27dev
m = Module()
counter = Signal(26)
m.comb += led.eq(counter[25])
m.sync += counter.eq(counter + 1)
plat.build(m)
APF51
#!/usr/local/bin/python3.4
# -*- coding: utf-8 -*-
from migen import *
from migen.fhdl import *
from migen.build.generic_platform import Pins, IOStandard
from migen.build.platforms import apf51
ios = [
("user_led", 0, Pins("J2:15"), IOStandard("LVCMOS33"))
]
plat = apf51.Platform()
plat.add_extension(ios)
led = plat.request("user_led", 0) # led pin on apf51dev
m = Module()
counter = Signal(26)
m.comb += led.eq(counter[25])
m.sync += counter.eq(counter + 1)
plat.build(m)
APF6SP
 |
Warning: This patch is required in Migen (adding apf6sp as platform) |
#!/usr/local/bin/python3.4
# -*- coding: utf-8 -*-
from migen import *
from migen.fhdl import *
from migen.build.generic_platform import Pins, IOStandard, Subsignal
from migen.build.platforms import apf6sp
ios = [ ("user_led", 0, Pins("HIROSE:D0")),]
plat = apf6sp.Platform()
plat.add_extension(ios)
led = plat.request("user_led", 0) # led pin on apf6sp_dev
m = Module()
plat.adding_pll_pcie_clk(m) # need a PLL on main clock
counter = Signal(26)
m.comb += led.eq(counter[25])
m.sync += counter.eq(counter + 1)
plat.build(m)
#XXX generate the rbf, should be integrated in platform build
import os
os.system("quartus_cpf -c build/top.sof top.rbf")
