Difference between revisions of "OPOS6UL SP Interfaces description"
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== FPGA Interrupt == | == FPGA Interrupt == | ||
Revision as of 07:52, 12 September 2018
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Contents
Introduction
This article describe the bus interface communication between the i.MX6UL(L) and the spartan6. In i.MX6UL(L) the bus used to make communication with the FPGA is named EIM for External Interface Module.
Simplified view
Default configuration on CSx
Clocks
Chip Select
Timings
HDL register access example
Pinout
FPGA Interrupt
FPGA configuration protocol
Links
- i.MX6UL(L) reference manual(PDF chapter 21 page 821)
