Difference between revisions of "A simple design with Wishbone bus"

From ArmadeusWiki
Jump to: navigation, search
m
Line 7: Line 7:
 
[http://armadeus.svn.sourceforge.net/viewvc/armadeus/trunk/firmware/wishbone_example/ tree].
 
[http://armadeus.svn.sourceforge.net/viewvc/armadeus/trunk/firmware/wishbone_example/ tree].
  
−
Description of wishbone structure for armadeus can be found [[FpgaArchitecture#Le_bus_Wishbone | here]] in french.
+
Description of wishbone structure for ARMadeus can be found [[FpgaArchitecture#Le_bus_Wishbone | here]] in french.
  
 
== General structure ==
 
== General structure ==
Line 18: Line 18:
 
is little bit more complicated (!).
 
is little bit more complicated (!).
  
−
When button is  pressed, the component ''Wb_button'' send interrupt signal to ''irq_mngr''. ''irq_mngr'' will toggle a flag and send interruption to  
+
When button is  pressed, the component ''button'' send interrupt signal to
 +
''irq_mngr''. ''irq_mngr'' will toggle a flag and send interruption to
 
'''i.mx''' processor. A Linux driver on '''i.mx''' will read ''irq_mngr'' and
 
'''i.mx''' processor. A Linux driver on '''i.mx''' will read ''irq_mngr'' and
−
acknowledge irq by writing '1' on a register. And finally, Linux driver will  
+
acknowledge irq by writing '1' on a register. And finally, Linux driver will
−
toggle led value by writing on led register.
+
toggle led value by writing on ''led'' register.
−
 
+
−
 
+
−
[[Image:Wb_buttonled_top.png|center|800px]]
+
  
 +
[[image:Wb_buttonled_top.png|center|frame|'''figure 1''' - ''Schematics of wishbone example''|500px]]
  
 
''imx_wrapper'', ''syscon'' and ''irq_mngr'' are standards
 
''imx_wrapper'', ''syscon'' and ''irq_mngr'' are standards
 
ARMadeus-Wishbone IPs that just been instantiated in our design.
 
ARMadeus-Wishbone IPs that just been instantiated in our design.
  
−
''Wb_button'' and ''Wb_led'' are simple slave component we want to
+
''button'' and ''led'' are simple slave component we want to
 
integrate in the FPGA.
 
integrate in the FPGA.
  
 
All these components are connected together with the 'glue logic' component ''intercon''.
 
All these components are connected together with the 'glue logic' component ''intercon''.
−
== Wrapper ==
 
−
Wrapper is used to convert i.MX interface signals into Wishbone signals.
 
  
−
== intercon ==  
+
=== Wrapper ===
 +
The [http://armadeus.svn.sourceforge.net/viewvc/armadeus/trunk/firmware/wishbone_example/src/imx9328_wb16_wrapper.vhd?revision=1108&view=markup wrapper] is used to convert i.MX interface signals into Wishbone signals. Table above show signals from i.MX and signals to wishbone conversion :
  
−
The intercon is a component used to manage signal between wishbone master and slaves component.
+
{| class="wikitable" style="text-align:center; width:50%;" border="1"
 +
|-
 +
! bgcolor=lightgray scope=col | i.MX signals
 +
! bgcolor=lightgray scope=col | function
 +
! bgcolor=lightgray scope=col | Wishbone signals
 +
|-
 +
| imx_address(12)
 +
| Address vector
 +
| wbm_address(13)
 +
|-
 +
| imx_data(16)
 +
| Data vector
 +
| wbm_writedata(16) and wbm_readdata(16)
 +
|-
 +
| imx_cs_n
 +
| Chip select
 +
| wbm_strobe and wbm_cycle
 +
|-
 +
| imx_oe_n
 +
| Read signal
 +
| /wbm_write
 +
|-
 +
| imx_eb3_n
 +
| Write signal
 +
| wbm_write
 +
|-
 +
| ?
 +
| Acknowledge
 +
| wbm_ack
 +
|}
 +
 
 +
=== Intercon ===
 +
 
 +
The [http://armadeus.svn.sourceforge.net/viewvc/armadeus/trunk/firmware/wishbone_example/src/imx9328_wb16_wrapper00_mwb16_intercon.vhd?revision=1108&view=markup  intercon] is a component used to manage signal between wishbone master and slaves component. This component decode Wishbone-master addresses and dispatch its to Wishbone-slave component.
 +
 
 +
[[image:Wb_intercon.png|center|frame|'''figure 2''' - ''Intercon internal structure''|500px]]
  
 
== Wishbone slave application components ==
 
== Wishbone slave application components ==
 +
 +
  
 
=== irq manager ===
 
=== irq manager ===
Line 51: Line 86:
 
This component is a simple 16-bit Wishbone slave output port, from [http://www.opencores.org/projects.cgi/web/wishbone/wbspec_b3.pdf wishbone specification example] (p110).
 
This component is a simple 16-bit Wishbone slave output port, from [http://www.opencores.org/projects.cgi/web/wishbone/wbspec_b3.pdf wishbone specification example] (p110).
  
−
[[Image:wbs_led.png|center|600px]]
+
[[image:wbs_led|center|frame|'''figure 3''' - ''Led internal structure''|600px]]
  
 
It is a simple register, that can be read and write. The led is controled with register pin 0.
 
It is a simple register, that can be read and write. The led is controled with register pin 0.
Line 59: Line 94:
 
Wb_button component, is like Wb_led but in read only and with an edge detector to rise irq.
 
Wb_button component, is like Wb_led but in read only and with an edge detector to rise irq.
  
−
[[Image:wbs_button.png|center|500px]]
+
[[image:wbs_button.png|center|frame|'''figure 4''' - ''Button internal structure''|500px]]
  
 
== Components drivers ==
 
== Components drivers ==

Revision as of 15:34, 6 March 2009

Page under construction...

Construction.png Informations on this page are not guaranteed !!

This article intended to explain how to design Wishbone compatible components with simple example. The VHDL code sources can be found in sourceforge tree.

Description of wishbone structure for ARMadeus can be found here in french.

General structure

The main functionality of this component is to do the same things that benoît project : switch on a led when a button is pressed.

But to learn about designing Wishbone component and linux driver, the design is little bit more complicated (!).

When button is pressed, the component button send interrupt signal to irq_mngr. irq_mngr will toggle a flag and send interruption to i.mx processor. A Linux driver on i.mx will read irq_mngr and acknowledge irq by writing '1' on a register. And finally, Linux driver will toggle led value by writing on led register.

figure 1 - Schematics of wishbone example

imx_wrapper, syscon and irq_mngr are standards ARMadeus-Wishbone IPs that just been instantiated in our design.

button and led are simple slave component we want to integrate in the FPGA.

All these components are connected together with the 'glue logic' component intercon.

Wrapper

The wrapper is used to convert i.MX interface signals into Wishbone signals. Table above show signals from i.MX and signals to wishbone conversion :

i.MX signals function Wishbone signals
imx_address(12) Address vector wbm_address(13)
imx_data(16) Data vector wbm_writedata(16) and wbm_readdata(16)
imx_cs_n Chip select wbm_strobe and wbm_cycle
imx_oe_n Read signal /wbm_write
imx_eb3_n Write signal wbm_write
 ? Acknowledge wbm_ack

Intercon

The intercon is a component used to manage signal between wishbone master and slaves component. This component decode Wishbone-master addresses and dispatch its to Wishbone-slave component.

figure 2 - Intercon internal structure

Wishbone slave application components

irq manager

Some component generate interrupts, irq manager is used to group these interrupts and generate one for i.MX.

wb_led

This component is a simple 16-bit Wishbone slave output port, from wishbone specification example (p110).

File:Wbs led
600px

It is a simple register, that can be read and write. The led is controled with register pin 0.

wb_button

Wb_button component, is like Wb_led but in read only and with an edge detector to rise irq.

figure 4 - Button internal structure

Components drivers

irq manager

led

button

Retrieved from "http://armadeus.org/wiki/index.php?title=A_simple_design_with_Wishbone_bus&oldid=6052"