IMX6-CycloneV interface description

Introduction

This article describe the bus interface configuration to communicate between i.MX6 processor and CycloneV FPGA. In i.MX6, the bus used to make communication with the FPGA is the PCI express.

Simplified view

figure 1 - i.MX6-PCIe bus description

Figure 1 is a simplified view of APF6 schematics, signals are :

• PCIE_CLK: 100Mhz differential pcie clock (PCIE_CLKN and PCIE_CLKP).
• PCIE_RX: Differential receive pcie signal lane0.
• PCIE_TX: Differential transmit pcie signal lane0

• coreclkout: 125Mhz (by default) clock generated by quartus hard PCIe ip-core, used to clock design by defaut.

FPGA pinout

FPGA pinout is the following :

# PCIE_RX
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hip_serial_rx_in0
set_location_assignment PIN_AA2 -to hip_serial_rx_in0
set_location_assignment PIN_AA1 -to "hip_serial_rx_in0(n)"
# PCIE_TX
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to hip_serial_tx_out0
set_location_assignment PIN_Y4 -to hip_serial_tx_out0
set_location_assignment PIN_Y3 -to "hip_serial_tx_out0(n)"
# PCIE_CLK
set_instance_assignment -name IO_STANDARD "1.5-V PCML" -to refclk_clk
set_location_assignment PIN_V4 -to refclk_clk
set_location_assignment PIN_U4 -to "refclk_clk(n)"

# nperst
set_location_assignment PIN_R17 -to nperst
# npor
set_location_assignment PIN_R16 -to npor

Links

• pci_debug: a usefull commands tool to access PCIe BARx