APF51 FPGA-IMX interface description

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This article describe the interface between the i.MX51 and the Spartan6 on APF51. Documentation of i.MX interface can be found in the i.MX reference manual, chapter 63, «Wireless External Interface Module (WEIM)».

Hardware

The detailed electronic schematics of APF51 FPGA interface can be found on this document page 15.

Signals used in the design are:

• BCLK: bus clock.
• EB[2]:
• CS2:
• CS1:
• LBA: Noted ADV in reference manual.
• DA[16]: Address/Data multiplexed bus.
• CLK0: General clock for FPGA, generated by the i.MX51
• OE: Read signal
• RW: Write signal
• DTACK:
• WAIT:

Mapping :

• CS1 -> B800_0000
• CS2 -> C000_0000