PCIe FPGA loading

Introduction

On APF6_SP it's possible to use the PCI express bus to configure fpga (cycloneV). This article describe how to do that.

Generate files

Quartus configuration

Your design must include the PCIe and CvP components. Once the project synthesized, open the menu

File -> Convert Programming Files ...

• In Output programming file select the programming file type: Raw Binary File (.rbf).
• In Input files to convert clic on Add Files... and add your binary.sof file.
• In Output programming file check the option Create CvP files (Generate binary.periph.rbf and binary.core.rbf)
• Click on Generate

You will get two files :

• binary.periph.rbf: peripheral config file to be loaded via serial config bus with uboot
• binary.core.rbf: core config file to be loaded via PCIe bus with Linux.