IMX51-Spartan6 interface description
Contents
Introduction
This article describe the bus interface configuration to communicate between i.MX51 processor and Spartan6 FPGA. In i.MX51, the bus used to make communication with the FPGA is named WEIM for Wireless Extension Interface Module. All description of this bus can be found under the i.MX51 reference manual in chapter 63 (page 3113).
Simplified view
Figure 1 is a simplified view of APF51 schematics (page 15), signals are :
- BCLK: i.MX51 burst clock used to clock the spartan6.
- DA[15:0] : Data/Address multiplexed bus.
- LBA : Noted ADV for ADdress Valid under the i.MX51 reference manual.
- EB0, EB1 : For Enable Byte, write signal for lower byte and upper byte on data bus.
- CS1 : Chip Select 1.
- CS2 : Chip Select 2.
- OE : For Output Enable bit, read signal. (Motorola way of bus)
- RW : Read/Write signal. (Intel way of bus)
- DTACK : Data acknoledge, for asynchronous access.
- WAIT : Wait signal used for some burst access.
Not part of WEIM bus :
- CLK0 : An i.MX51 output clock (not used ).
- FPGA_INITB : used by default for interrupts (GPIO4_11).
Signals in bold are signals used in default configuration.
Default configuration on CS1
Clock
The clock used to clock the fpga is BCLK (IO_L29P_GCLK3_2 on Spartan6) and is configured to 95 MHz.
Chip Select
By default the chip select 1 (CS1) is used for communication. The address domain corresponding to this chip select can be found in i.MX51 reference manual in chapter 2 (Memory Map page 65).
| Start Address | End Address | Size | Region |
|---|---|---|---|
| B800_0000 | BFFF_FFFF | 128M | CS1 (Flash) 128M |
| C000_0000 | C7FF_FFFF | 128M | CS2 (Flash) 128M |
It's possible to use the second chip select (CS2) to extend memory domain or to use different timing configuration with the same Address/Data bus signals. The default bus configuration for the APF51 can be found in the file apf51.h in u-boot sources : buildroot/target/device/armadeus/apf51/apf51-u-boot-2010.03.h
Especially these lines :
#define CONFIG_FPGA_GCR1_VALUE 0x019100bf
#define CONFIG_FPGA_GCR2_VALUE 0x00000000
#define CONFIG_FPGA_RCR1_VALUE 0x04000010
#define CONFIG_FPGA_RCR2_VALUE 0x00000000
#define CONFIG_FPGA_WCR1_VALUE 0x04000008
#define CONFIG_FPGA_WCR2_VALUE 0x00000000
 |
Note: Do not forget to do :
$ make u-boot-dirclean $ make To test your modification under the apf51-u-boot-2010.03.h file |
It is not necessary to modify apf51.h file and recompile U-Boot for WEIM timings test, register can be read/written via U-Boot or Linux.
To access these register with U-Boot or Linux, use the address given under the reference manual in WEIM register descriptions (63.4.3 Register Descriptions).
| |
Note: The 0xBASE value is given in chapter 2 "Memory Map" (page 65) : 0xBASE -> 0x83FD8000 |
Timings
Following chronograms represents WEIM read and write configured for APF51.
FPGA side
By default, the wishbone bus is used under the spartan6 fpga. Then a WEIM to Wishbone wrapper is used, this wrapper is available under POD default libraries in wrappers lib. The component is named imx51_wb16_wrapper.
The FPGA interrupt
By default under POD the pin FPGA_INITB (gpio4_11) is used for the interrupts manager irq_mngr. For simple user application the gpio can be used with the GPIOlib interface, the gpio number will then be (4-1)x32+11 = 107.
