APF27 FPGA-IMX interface description

This article describe the interface between IMX and Spartan3A on APF27. Documentation of i.MX interface can be found in reference manual chapter 17 «Wireless External Interface Module (WEIM)».

Hardware

Electronic schematic of apf27 fpga interface can be found on this document page 11. Simplified schema is describe bellow on figure 1.

figure 1 - FPGA-i.MXL wiring

Signals used in design are :

• CLKO : Clock generated by i.MX used as general clock by the fpga.
• DATA[16] : 16 bits data bus.
• ADDR[13] : 12 bits data bus, least significant bit (ADDR[0]) is not used because only word access are done.
• CS4N_DTACK: Chip Select 4 or Data Transmit ACKnowledge.
• CS5,CS1 : Chip Select 5 and 1.
• EB0N and EB1N: For Enable Byte, write signal for lower byte and upper byte on data bus.
• OEN : For Output Enable bit, read signal.
• DMA_GRANT# and DMA_REQ# : Signals to use DMA on i.MX.