DDR3-CycloneV interface description

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Revision as of 13:29, 15 June 2015 by FabienM (Talk | contribs) (→‎Pinout placement)

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Introduction

2 RAMs are connected to CycloneV's APF6_SP.

Parameters

  • DDR3:
MT41K128M16JT-125
part MT41K128M16JT-125
type DDR3L
Speed 750Mhz
timings See verilog model provided by micron
JEDEC JEDEC DDR3-1600 -> JEDEC DDR3-1G6 2GB x8
Chip size 2048Mbits -> 128M x 16bits

Simplified view

Page under construction...

Construction.png Informations on this page are not guaranteed !!

IO

Pinout placement

set_location_assignment PIN_C11 -to mem_a[0]
set_location_assignment PIN_B11 -to mem_a[1]
set_location_assignment PIN_A8 -to mem_a[2]
set_location_assignment PIN_A7 -to mem_a[3]
set_location_assignment PIN_D11 -to mem_a[4]
set_location_assignment PIN_E11 -to mem_a[5]
set_location_assignment PIN_F8 -to mem_a[6]
set_location_assignment PIN_E7 -to mem_a[7]
set_location_assignment PIN_D9 -to mem_a[8]
set_location_assignment PIN_D8 -to mem_a[9]
set_location_assignment PIN_B6 -to mem_a[10]
set_location_assignment PIN_B5 -to mem_a[11]
set_location_assignment PIN_C8 -to mem_a[12]
set_location_assignment PIN_B8 -to mem_a[13]
set_location_assignment PIN_H6 -to mem_a[14]

set_location_assignment PIN_C9 -to mem_ba[2]
set_location_assignment PIN_C10 -to mem_ba[1]
set_location_assignment PIN_C6 -to mem_ba[0]

set_location_assignment PIN_A10 -to mem_cas_n[0]
set_location_assignment PIN_J9 -to mem_ck[0]
set_location_assignment PIN_J8 -to mem_ck_n[0]
set_location_assignment PIN_H8 -to mem_cs_n[0]

set_location_assignment PIN_C21 -to mem_dm[2]
set_location_assignment PIN_C19 -to mem_dm[1]
set_location_assignment PIN_A15 -to mem_dm[0]

set_location_assignment PIN_C20 -to mem_dq[23]
set_location_assignment PIN_B20 -to mem_dq[22]
set_location_assignment PIN_D18 -to mem_dq[21]
set_location_assignment PIN_E17 -to mem_dq[20]
set_location_assignment PIN_A22 -to mem_dq[19]
set_location_assignment PIN_A20 -to mem_dq[18]
set_location_assignment PIN_E16 -to mem_dq[17]
set_location_assignment PIN_D17 -to mem_dq[16]

set_location_assignment PIN_C18 -to mem_dq[15]
set_location_assignment PIN_B16 -to mem_dq[14]
set_location_assignment PIN_C16 -to mem_dq[13]
set_location_assignment PIN_C15 -to mem_dq[12]
set_location_assignment PIN_A17 -to mem_dq[11]
set_location_assignment PIN_B18 -to mem_dq[10]
set_location_assignment PIN_F15 -to mem_dq[9]
set_location_assignment PIN_E14 -to mem_dq[8]
set_location_assignment PIN_A14 -to mem_dq[7]
set_location_assignment PIN_C14 -to mem_dq[6]
set_location_assignment PIN_D13 -to mem_dq[5]
set_location_assignment PIN_C13 -to mem_dq[4]
set_location_assignment PIN_B13 -to mem_dq[3]
set_location_assignment PIN_B12 -to mem_dq[2]
set_location_assignment PIN_E12 -to mem_dq[1]
set_location_assignment PIN_F12 -to mem_dq[0]

set_location_assignment PIN_G15 -to mem_dqs[2]
set_location_assignment PIN_G14 -to mem_dqs_n[2]

set_location_assignment PIN_G12 -to mem_dqs[1]
set_location_assignment PIN_H12 -to mem_dqs_n[1]

set_location_assignment PIN_H9 -to mem_dqs[0]
set_location_assignment PIN_G8 -to mem_dqs_n[0]

set_location_assignment PIN_A13 -to mem_odt[0]
set_location_assignment PIN_B15 -to mem_cke[0]
set_location_assignment PIN_A9 -to mem_ras_n[0]
set_location_assignment PIN_E6 -to mem_we_n[0]
set_location_assignment PIN_B22 -to mem_reset_n
set_location_assignment PIN_A12 -to oct_rzqin

set_location_assignment PIN_T20 -to global_reset_n # Pulled-up on apf6sp
set_location_assignment PIN_H10 -to pll_ref_clk # Not Connected on apf6sp
set_location_assignment PIN_R16 -to soft_reset_n # Pulled-up on apf6sp

# Random pinout (not used)
set_location_assignment PIN_Y16 -to drv_status_fail
set_location_assignment PIN_H18 -to drv_status_pass
set_location_assignment PIN_V18 -to drv_status_test_complete
set_location_assignment PIN_J17 -to local_cal_fail
set_location_assignment PIN_J19 -to local_cal_success
set_location_assignment PIN_AA7 -to local_init_done

Technology pinout

set_instance_assignment -name IO_STANDARD "SSTL-135" -to oct_rzqin -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_dq[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dq[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_dq[1] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dq[1] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[1] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_dq[2] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dq[2] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[2] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_dq[3] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dq[3] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[3] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_dq[4] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dq[4] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[4] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_dq[5] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dq[5] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[5] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_dq[6] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dq[6] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[6] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_dq[7] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dq[7] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[7] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_dq[8] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dq[8] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[8] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_dq[9] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dq[9] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[9] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_dq[10] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dq[10] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[10] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_dq[11] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dq[11] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[11] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_dq[12] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dq[12] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[12] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_dq[13] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dq[13] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[13] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_dq[14] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dq[14] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[14] -tag __ddr3_contr_example_if0_p0

set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_dq[15] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dq[15] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[15] -tag __ddr3_contr_example_if0_p0

set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_dq[16] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dq[16] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[16] -tag __ddr3_contr_example_if0_p0

set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_dq[17] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dq[17] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[17] -tag __ddr3_contr_example_if0_p0

set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_dq[18] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dq[18] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[18] -tag __ddr3_contr_example_if0_p0

set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_dq[19] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dq[19] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[19] -tag __ddr3_contr_example_if0_p0

set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_dq[20] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dq[20] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[20] -tag __ddr3_contr_example_if0_p0

set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_dq[21] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dq[21] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[21] -tag __ddr3_contr_example_if0_p0

set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_dq[22] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dq[22] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[22] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_dq[23] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dq[23] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dq[23] -tag __ddr3_contr_example_if0_p0

set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.35-V SSTL" -to mem_dqs[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dqs[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dqs[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.35-V SSTL" -to mem_dqs_n[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dqs_n[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dqs_n[0] -tag __ddr3_contr_example_if0_p0

set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.35-V SSTL" -to mem_dqs[1] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dqs[1] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dqs[1] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.35-V SSTL" -to mem_dqs_n[1] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dqs_n[1] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dqs_n[1] -tag __ddr3_contr_example_if0_p0

set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.35-V SSTL" -to mem_dqs[2] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dqs[2] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dqs[2] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.35-V SSTL" -to mem_dqs_n[2] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 40 OHM WITH CALIBRATION" -to mem_dqs_n[2] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dqs_n[2] -tag __ddr3_contr_example_if0_p0

set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.35-V SSTL" -to mem_ck[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to mem_ck[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.35-V SSTL" -to mem_ck_n[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to mem_ck_n[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_a[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to mem_a[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_a[10] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to mem_a[10] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_a[11] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to mem_a[11] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_a[12] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to mem_a[12] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_a[13] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to mem_a[13] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_a[14] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to mem_a[14] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_a[1] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to mem_a[1] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_a[2] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to mem_a[2] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_a[3] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to mem_a[3] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_a[4] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to mem_a[4] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_a[5] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to mem_a[5] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_a[6] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to mem_a[6] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_a[7] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to mem_a[7] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_a[8] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to mem_a[8] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_a[9] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to mem_a[9] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_ba[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to mem_ba[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_ba[1] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to mem_ba[1] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_ba[2] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to mem_ba[2] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_cas_n[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to mem_cas_n[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_cke[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to mem_cke[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_cs_n[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to mem_cs_n[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_odt[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to mem_odt[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_ras_n[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to mem_ras_n[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_we_n[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to mem_we_n[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_reset_n -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITHOUT CALIBRATION" -to mem_reset_n -tag __ddr3_contr_example_if0_p0

set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_dm[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dm[0] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_dm[1] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dm[1] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name IO_STANDARD "SSTL-135" -to mem_dm[2] -tag __ddr3_contr_example_if0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 40 OHM WITH CALIBRATION" -to mem_dm[2] -tag __ddr3_contr_example_if0_p0

set_instance_assignment -name IO_STANDARD "SSTL-135" -to pll_ref_clk -tag __ddr3_contr_example_if0_p0

Clock

The hard controller IP «DDR3 SDRAM Controller with UniPHY» require using and external oscillator to clock it. On APF6_SP, the all CycloneV fpga is clocked with the PCIe clock at 125Mhz by default.

To force Quartus to use the coreclkout as input clock for DDR3 controller a little hack must be done after HDL code is generated.

The DDR3 clock hack

Note Note: If you include the .qsys under your Quartus project, Quartus will regenerate all the Qsys HDL/TCL code each times you synthesize your design, and will erase the modification.
  1. Generate the design with Qsys
    1. Connect the pll_ref_clk of IP DDR3 SDRAM Controller with UniPHY on coreclkout of Avalon-MM Cyclone V Hard IP for PCI Express.
    2. Do all connections you need/want
    3. Generate the HDL code with Finish button.
  2. Under Quartus include the file your_project.qip and not your_project.qsys
    1. Find the file named *_p0_pin_map.tcl :
      $ find . -name "*_p0_pin_map.tcl"
    2. It must be under directory named your_project/synthesis/submodules/
    3. Edit it and looking for line begining with : 
      proc qsys_pattern_mem_if_ddr3_emif_0_p0_get_input_clk_id { pll_output_node_id } {
    4. Add this line at the begining of function :
      return $pll_output_node_id
    5. Then synthesize all.

Links

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