APF6 SP Interfaces description
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<< FPGA general page
Contents
1
Introduction
2
i.MX6 to CycloneV
3
DDR3 to CycloneV
4
Pinouts
5
Howto
6
Links
Introduction
This page describe the FPGA interfaces for APF6_SP.
i.MX6 to CycloneV
IMX6-CycloneV interface description (PCIe)
DDR3 to CycloneV
DDR3-CycloneV interface description
Pinouts
Pinout on apf6sp hirose connector
Howto
The full FPGA howto for the APF6_sp, with PCIe, DDR3 and I/O
Links
Categories
:
APF6 SP
FPGA
CycloneV
Quartus
Qsys
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