Wb button.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

---------------------------------------------------------------------------
Entity Wb_button is 
---------------------------------------------------------------------------
	port 
	(
		-- global signals
		wbc_candr_reset : in std_logic ;
		wbc_candr_clk 	: in std_logic ;
		-- Wishbone signals
		wbs_sbutton_readdata  : out std_logic_vector( 15 downto 0);
		wbs_sbutton_strobe    : in std_logic ;
		wbs_sbutton_write	  : in std_logic ;
		wbs_sbutton_ack	      : out std_logic;
		-- irq
		wbs_sbutton_irq : out std_logic ;
		-- fpga input
		gls_button_export 		: in std_logic 
	);
end entity;


---------------------------------------------------------------------------
Architecture Wb_button_1 of Wb_button is
	---------------------------------------------------------------------------
	signal button_r : std_logic ;
	signal reg : std_logic_vector( 15 downto 0);
begin

	-- connect button
	cbutton : process(wbc_candr_clk,wbc_candr_reset)
	begin
		if wbc_candr_reset = '1' then
			reg <= (others => '0');
		elsif rising_edge(wbc_candr_clk) then
			reg <= "000000000000000"&gls_button_export;
		end if;
	end process cbutton;


	-- rise interruption
	pbutton : process(wbc_candr_clk,wbc_candr_reset)
	begin
		if wbc_candr_reset = '1' then
			wbs_sbutton_irq <= '0';
			button_r <= '0';
		elsif rising_edge(wbc_candr_clk) then
			if button_r /= gls_button_export then
				wbs_sbutton_irq <= '1';
			else
				wbs_sbutton_irq <= '0';
			end if;
			button_r <= gls_button_export;
		end if;
	end process pbutton;

	-- register reading process
	pread : process(wbc_candr_clk,wbc_candr_reset)
	begin
		if(wbc_candr_reset = '1') then
			wbs_sbutton_ack <= '0';
			wbs_sbutton_readdata <= (others => '0');
		elsif(falling_edge(wbc_candr_clk)) then
			wbs_sbutton_ack <= '1';
			if(wbs_sbutton_strobe = '1' and wbs_sbutton_write = '0')then
				wbs_sbutton_readdata <= reg;
			end if;
		end if;
	end process pread;

end architecture Wb_button_1;