I2C
This page will summarize the informations to use the I2C bus on our boards.
Contents
Overview
The I2C bus is a simple & widely used two wires synchronous bus. It has been developped by Philips (now NXP).
The standard frequency is 100kHz but 400kHz devices can be found (for example the i.MX).
Single and multi masters are supported. Only the single master configuration will be discussed here.
The bus is based on two signals: SDA and SCL.
- SDA: bidirectional line for data
- SCL: unidirectional line for the clock (provided by the master)
Details can be found in the specification here.
Linux configuration
By default the I2C bus is activated in the Armadeus distrib. If you need to deactivate it, take a look at the linux menuconfig (make linux-menuconfig)
Linux user space C code
Kernel source has a good documentation on using i2c bus through /dev with C program, it can be found in kernel source directory Documentation/i2c/dev-interface.
You can find a sample code under target/packages/ch7024ctrl/ of the Armadeus distribution ( or here through SF's SVN browsing )
Tested I2C chips
APF9328 I2C bus logic 5v level adaptation (if necessary)
On the APF9328 the I2C bus has a 3,3V logic level so if you want to use 5V I2C devices you have to add a level converter, for example a PCA9306 from NXP:
- Connect pin 1 to the local GND
- Connect pin 2 to the local 3.3V
- Connect pin 3 to the SCL output of the APF
- Connect pin 4 to the SDA input/ouput of the APF
- Connect pin 7 and 8 together and the add a 200K resistor in parallel to a 100nF capacitor to GND
- Connect a pullup of 1.7K to the 5V SCL line (pin 6)
- Connect a pullup of 1.7K to the 5V SDA line (pin 5)
For more details, take a look at the PCA9306 datasheet. This chip is the one that can be mounted by users on the DevFull board.
As a low-cost alternative, a level shifter can be built with a pair of N-channel mosfets (such as a BS170). See the Application Note 97055.
