SP VISION

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Introduction

The SP_Vision board is an extension of APF27Dev and APF51Dev with a Spartan6 and two DDR. It is designed for real-time video processing.

Configure the Spartan6 with apf27-Dev

Spartan6 selectmap configuration port is plugged on generic IO of APF27 Spartan3 FPGA. Then, to configure Spartan6, a specific virtual component is required under Spartan3. This virtual component is available under POD components library and is named spartan_selectmap. This component must be added to your Spartan3 design to enable SP_vision Spartan6 configuration.

A simple Spartan3 design is available under ARMadeus project tree firmware/sp_vision_config/ to simplify sp_vision config. The design can be synthetized with ISE using the TCL script firmware/sp_vision_config/synthesis/testconfig.tcl. The already synthetized bitstream is also available under firmware/sp_vision_config/bitstream/.

Then to configure Spartan6 :

• first configure APF27's Spartan3:

BIOS> tftpboot ${loadaddr} top_testconfig.bit
BIOS> fpga load 0 ${loadaddr} 2486f

• then configure the second FPGA using loadsecond operator:

BIOS> tftpboot ${loadaddr} spartan6_example_top.bit
BIOS> fpga loadsecond 1 ${loadaddr} 16a674 D6000000 1