Wb led.vhd

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

-----------------------------------------------------------------------
	Entity Wb_led is 
-----------------------------------------------------------------------
    port 
    (
		-- Syscon signals
		wbc_candr_reset : in std_logic ;
		wbc_candr_clk	  : in std_logic ;
		-- Wishbone signals
		wbs_sled_writedata : in std_logic_vector( 15 downto 0);
		wbs_sled_readdata  : out std_logic_vector( 15 downto 0);
		wbs_sled_strobe    : in std_logic ;
		wbs_sled_write	  : in std_logic ;
		wbs_sled_ack	      : out std_logic;
		-- out signals
		gls_led_export : out std_logic 
    );
end entity;


-----------------------------------------------------------------------
Architecture Wb_led_1 of Wb_led is
-----------------------------------------------------------------------
	signal reg : std_logic_vector( 15 downto 0);
begin

-- connect led
gls_led_export <= reg(0);

-- manage register
reg_bloc : process(wbc_candr_clk,wbc_candr_reset)
begin
	if wbc_candr_reset = '1' then 
		reg <= (others => '0');
	elsif rising_edge(wbc_candr_clk) then
		if ((wbs_sled_strobe and wbs_sled_write) = '1' ) then
			reg <= wbs_sled_writedata;
		else
			reg <= reg;
		end if;
	end if;

end process reg_bloc;

wbs_sled_ack <= wbs_sled_strobe;
wbs_sled_readdata <= reg;

end architecture Wb_led_1;